From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MtLqZ-0003UY-JU for qemu-devel@nongnu.org; Thu, 01 Oct 2009 09:37:27 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MtLqT-0003U3-JS for qemu-devel@nongnu.org; Thu, 01 Oct 2009 09:37:25 -0400 Received: from [199.232.76.173] (port=40138 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MtLqT-0003Tx-EH for qemu-devel@nongnu.org; Thu, 01 Oct 2009 09:37:21 -0400 Received: from mx1.redhat.com ([209.132.183.28]:52584) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MtLqT-00020Q-5P for qemu-devel@nongnu.org; Thu, 01 Oct 2009 09:37:21 -0400 Date: Thu, 1 Oct 2009 15:37:16 +0200 From: Gleb Natapov Subject: Re: [Qemu-devel] [PATCH 57/61] ioapic: add callback when entry is set or ioapic is reset Message-ID: <20091001133716.GT9832@redhat.com> References: <1254305917-14784-1-git-send-email-yamahata@valinux.co.jp> <1254305917-14784-58-git-send-email-yamahata@valinux.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1254305917-14784-58-git-send-email-yamahata@valinux.co.jp> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Isaku Yamahata Cc: qemu-devel@nongnu.org On Wed, Sep 30, 2009 at 07:18:33PM +0900, Isaku Yamahata wrote: > Add hooks to ioapic. > This is necessary for pci interrupt routing mode from > PIC mode to IO APIC mode. According to my very brief looking at ICH9 spec switching from PIC mode to IO APIC mode is done separately for each PIRQ by setting bit 7 of PIRQ[n]_ROUT register to 1. This callback looks completely out of place. > > Signed-off-by: Isaku Yamahata > --- > hw/ioapic.c | 20 +++++++++++++++++++- > hw/pc.h | 2 ++ > 2 files changed, 21 insertions(+), 1 deletions(-) > > diff --git a/hw/ioapic.c b/hw/ioapic.c > index a9a8e00..882ca9d 100644 > --- a/hw/ioapic.c > +++ b/hw/ioapic.c > @@ -53,8 +53,16 @@ struct IOAPICState { > > uint32_t irr; > uint64_t ioredtbl[IOAPIC_NUM_PINS]; > + ioapic_update_fn update_fn; > + void *opaque; > }; > > +static void ioapic_callback(IOAPICState *s, int reset) > +{ > + if (s->update_fn) > + s->update_fn(s->opaque, reset); > +} > + > static void ioapic_service(IOAPICState *s) > { > uint8_t i; > @@ -186,6 +194,7 @@ static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t va > s->ioredtbl[index] &= ~0xffffffffULL; > s->ioredtbl[index] |= val; > } > + ioapic_callback(s, 0); > ioapic_service(s); > } > } > @@ -210,6 +219,8 @@ static void ioapic_reset(void *opaque) > IOAPICState *s = opaque; > int i; > > + ioapic_callback(s, 1); > + > memset(s, 0, sizeof(*s)); > for(i = 0; i < IOAPIC_NUM_PINS; i++) > s->ioredtbl[i] = 1 << 16; /* mask LVT */ > @@ -227,13 +238,15 @@ static CPUWriteMemoryFunc * const ioapic_mem_write[3] = { > ioapic_mem_writel, > }; > > -qemu_irq *ioapic_init(void) > +qemu_irq *ioapic_init_with_arg(ioapic_update_fn update_fn, void *opaque) > { > IOAPICState *s; > qemu_irq *irq; > int io_memory; > > s = qemu_mallocz(sizeof(IOAPICState)); > + s->update_fn = update_fn; > + s->opaque = opaque; > ioapic_reset(s); > > io_memory = cpu_register_io_memory(ioapic_mem_read, > @@ -246,3 +259,8 @@ qemu_irq *ioapic_init(void) > > return irq; > } > + > +qemu_irq *ioapic_init(void) > +{ > + return ioapic_init_with_arg(NULL, NULL); > +} > diff --git a/hw/pc.h b/hw/pc.h > index 7577956..44eac49 100644 > --- a/hw/pc.h > +++ b/hw/pc.h > @@ -52,6 +52,8 @@ int apic_accept_pic_intr(CPUState *env); > void apic_deliver_pic_intr(CPUState *env, int level); > int apic_get_interrupt(CPUState *env); > qemu_irq *ioapic_init(void); > +typedef void (*ioapic_update_fn)(void *opaque, int reset); > +qemu_irq *ioapic_init_with_arg(ioapic_update_fn update_fn, void *opaque); > void apic_reset_irq_delivered(void); > int apic_get_irq_delivered(void); > > -- > 1.6.0.2 > > -- Gleb.