From mboxrd@z Thu Jan  1 00:00:00 1970
From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Subject: Re: Re: VT-d on Asus P7P55D-Evo: IOMMU not supported
Date: Fri, 9 Apr 2010 09:48:18 -0400
Message-ID: <20100409134818.GA26880@phenom.dumpdata.com>
References: <3CFA80FC-7C88-4CDF-B613-FAE24A57031A@xs4all.nl>
	<ED3036A092A28F4C91B0B4360DD128EABE0C0654@shzsmsx502.ccr.corp.intel.com>
	<201003312051.02146.mark.hurenkamp@xs4all.nl>
	<hp0idd$toh$1@dough.gmane.org> <20100401055024.GC1878@reaktio.net>
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To: Pasi =?iso-8859-1?Q?K=E4rkk=E4inen?= <pasik@iki.fi>
Cc: xen-devel@lists.xensource.com, Christian Tramnitz <chris.ace@gmx.net>
List-Id: xen-devel@lists.xenproject.org

On Thu, Apr 01, 2010 at 08:50:24AM +0300, Pasi K=E4rkk=E4inen wrote:
> On Thu, Apr 01, 2010 at 12:29:03AM +0200, Christian Tramnitz wrote:
> > 31.03.2010 22:51, Mark Hurenkamp wrote:
> > > Asus doesn't seem to pay much attention to VT-d issues with their P=
55
> > > boards, i couldn't find any indication that they are working on it.
> > > I tried to submit a tech support question, but it requires a serial=
 number,
> > > which i seem to be unable to locate on the board.
> >=20
> > Even if you find the serial and open the support case there will be n=
o
> > meaningful answer just "Linux is not supported". Been there, done tha=
t....
> >=20
>=20
> Please see here:=20
> http://wiki.xensource.com/xenwiki/XenPCIpassthrough
>=20
> Especially this:=20
> "Intel developers also want to know about broken IOMMU/VT-d BIOS implem=
entations, see this email: http://lists.xensource.com/archives/html/xen-d=
evel/2010-01/msg00841.html, so let them know all the details about your h=
ardware and software if you have broken BIOS. "

This just got posted on LKML that might shed the light on why certain
motherboards have VT-d working i7 but not with i5 CPUs:

(https://lists.linux-foundation.org/pipermail/iommu/2010-April/002268.htm=
l):
"
When using iommu_domain_alloc with the Intel iommu, the domain address wi=
dth=20
is always initialized to 48 bits (agaw 2).  This domain->agaw value is th=
en=20
used by pfn_to_dma_pte to (always) build a 4 level page table.  However, =
not=20
all systems support iommu width of 48 or 4 level page tables.  In particu=
lar,=20
the Core i5-660 and i5-670 support an address width of 36 bits (not 39!),=
 an=20
agaw of only 1, and only 3 level page tables.

My patch delays the domain initialization until the first iommu_attach_de=
vice,
...