From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rusty Russell Subject: Re: virtio: put last_used and last_avail index into ring itself. Date: Mon, 10 May 2010 12:41:56 +0930 Message-ID: <201005101241.57237.rusty__44149.3426370018$1273481792$gmane$org@rustcorp.com.au> References: <201005071235.40590.rusty@rustcorp.com.au> <20100509085733.GD16775@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20100509085733.GD16775@redhat.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: virtualization-bounces@lists.linux-foundation.org Errors-To: virtualization-bounces@lists.linux-foundation.org To: "Michael S. Tsirkin" Cc: Eric Dumazet , kvm@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, virtualization@lists.linux-foundation.org, linux-mm@kvack.org, s.hetze@linux-ag.com, hpa@zytor.com, Daniel Walker , mingo@elte.hu, akpm@linux-foundation.org List-Id: virtualization@lists.linuxfoundation.org On Sun, 9 May 2010 06:27:33 pm Michael S. Tsirkin wrote: > On Fri, May 07, 2010 at 12:35:39PM +0930, Rusty Russell wrote: > > Then there's padding to page boundary. That puts us on a cacheline again > > for the used ring; also 2 bytes per entry. > > > > Hmm, is used ring really 2 bytes per entry? Err, no, I am an idiot. > /* u32 is used here for ids for padding reasons. */ > struct vring_used_elem { > /* Index of start of used descriptor chain. */ > __u32 id; > /* Total length of the descriptor chain which was used (written to) */ > __u32 len; > }; > > struct vring_used { > __u16 flags; > __u16 idx; > struct vring_used_elem ring[]; > }; OK, now I get it. Sorry, I was focussed on the avail ring. > I thought that used ring has 8 bytes per entry, and that struct > vring_used is aligned at page boundary, this > would mean that ring element is at offset 4 bytes from page boundary. > Thus with cacheline size 128 bytes, each 4th element crosses > a cacheline boundary. If we had a 4 byte padding after idx, each > used element would always be completely within a single cacheline. I think the numbers are: every 16th entry hits two cachelines. So currently the first 15 entries are "free" (assuming we hit the idx cacheline anyway), then 1 in 16 cost 2 cachelines. That makes the aligned version win when N > 240. But, we access the array linearly. So the extra cacheline cost is in fact amortized. I doubt it could be measured, but maybe vring_get_buf() should prefetch? While you're there, we could use an & rather than a mod on the calculation, which may actually be measurable :) Cheers, Rusty.