From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Nadav Har'El" Subject: [PATCH 12/24] Add VMCS fields to the vmcs12 Date: Sun, 13 Jun 2010 15:28:43 +0300 Message-ID: <201006131228.o5DCSh8O013014@rice.haifa.ibm.com> References: <1276431753-nyh@il.ibm.com> Cc: kvm@vger.kernel.org To: avi@redhat.com Return-path: Received: from mtagate7.de.ibm.com ([195.212.17.167]:39989 "EHLO mtagate7.de.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751891Ab0FMM2q (ORCPT ); Sun, 13 Jun 2010 08:28:46 -0400 Received: from d12nrmr1607.megacenter.de.ibm.com (d12nrmr1607.megacenter.de.ibm.com [9.149.167.49]) by mtagate7.de.ibm.com (8.13.1/8.13.1) with ESMTP id o5DCSjDv010244 for ; Sun, 13 Jun 2010 12:28:45 GMT Received: from d12av03.megacenter.de.ibm.com (d12av03.megacenter.de.ibm.com [9.149.165.213]) by d12nrmr1607.megacenter.de.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id o5DCSjEg1290290 for ; Sun, 13 Jun 2010 14:28:45 +0200 Received: from d12av03.megacenter.de.ibm.com (loopback [127.0.0.1]) by d12av03.megacenter.de.ibm.com (8.12.11.20060308/8.13.3) with ESMTP id o5DCSiI8024589 for ; Sun, 13 Jun 2010 14:28:45 +0200 Sender: kvm-owner@vger.kernel.org List-ID: In this patch we add to vmcs12 (the VMCS that L1 keeps for L2) all the standard VMCS fields. These fields are encapsulated in a struct shadow_vmcs. Later patches will enable L1 to read and write these fields using VMREAD/ VMWRITE, and they will be used during a VMLAUNCH/VMRESUME in preparing a real VMCS for running L2. Signed-off-by: Nadav Har'El --- --- .before/arch/x86/kvm/vmx.c 2010-06-13 15:01:29.000000000 +0300 +++ .after/arch/x86/kvm/vmx.c 2010-06-13 15:01:29.000000000 +0300 @@ -117,6 +117,136 @@ struct shared_msr_entry { u64 mask; }; +/* shadow_vmcs is a structure used in nested VMX for holding a copy of all + * standard VMCS fields. It is used for emulating a VMCS for L1 (see vmcs12), + * and also for easier access to VMCS data (see l1_shadow_vmcs). + */ +struct __attribute__ ((__packed__)) shadow_vmcs { + u16 virtual_processor_id; + u16 guest_es_selector; + u16 guest_cs_selector; + u16 guest_ss_selector; + u16 guest_ds_selector; + u16 guest_fs_selector; + u16 guest_gs_selector; + u16 guest_ldtr_selector; + u16 guest_tr_selector; + u16 host_es_selector; + u16 host_cs_selector; + u16 host_ss_selector; + u16 host_ds_selector; + u16 host_fs_selector; + u16 host_gs_selector; + u16 host_tr_selector; + u64 io_bitmap_a; + u64 io_bitmap_b; + u64 msr_bitmap; + u64 vm_exit_msr_store_addr; + u64 vm_exit_msr_load_addr; + u64 vm_entry_msr_load_addr; + u64 tsc_offset; + u64 virtual_apic_page_addr; + u64 apic_access_addr; + u64 ept_pointer; + u64 guest_physical_address; + u64 vmcs_link_pointer; + u64 guest_ia32_debugctl; + u64 guest_ia32_pat; + u64 guest_pdptr0; + u64 guest_pdptr1; + u64 guest_pdptr2; + u64 guest_pdptr3; + u64 host_ia32_pat; + u32 pin_based_vm_exec_control; + u32 cpu_based_vm_exec_control; + u32 exception_bitmap; + u32 page_fault_error_code_mask; + u32 page_fault_error_code_match; + u32 cr3_target_count; + u32 vm_exit_controls; + u32 vm_exit_msr_store_count; + u32 vm_exit_msr_load_count; + u32 vm_entry_controls; + u32 vm_entry_msr_load_count; + u32 vm_entry_intr_info_field; + u32 vm_entry_exception_error_code; + u32 vm_entry_instruction_len; + u32 tpr_threshold; + u32 secondary_vm_exec_control; + u32 vm_instruction_error; + u32 vm_exit_reason; + u32 vm_exit_intr_info; + u32 vm_exit_intr_error_code; + u32 idt_vectoring_info_field; + u32 idt_vectoring_error_code; + u32 vm_exit_instruction_len; + u32 vmx_instruction_info; + u32 guest_es_limit; + u32 guest_cs_limit; + u32 guest_ss_limit; + u32 guest_ds_limit; + u32 guest_fs_limit; + u32 guest_gs_limit; + u32 guest_ldtr_limit; + u32 guest_tr_limit; + u32 guest_gdtr_limit; + u32 guest_idtr_limit; + u32 guest_es_ar_bytes; + u32 guest_cs_ar_bytes; + u32 guest_ss_ar_bytes; + u32 guest_ds_ar_bytes; + u32 guest_fs_ar_bytes; + u32 guest_gs_ar_bytes; + u32 guest_ldtr_ar_bytes; + u32 guest_tr_ar_bytes; + u32 guest_interruptibility_info; + u32 guest_activity_state; + u32 guest_sysenter_cs; + u32 host_ia32_sysenter_cs; + unsigned long cr0_guest_host_mask; + unsigned long cr4_guest_host_mask; + unsigned long cr0_read_shadow; + unsigned long cr4_read_shadow; + unsigned long cr3_target_value0; + unsigned long cr3_target_value1; + unsigned long cr3_target_value2; + unsigned long cr3_target_value3; + unsigned long exit_qualification; + unsigned long guest_linear_address; + unsigned long guest_cr0; + unsigned long guest_cr3; + unsigned long guest_cr4; + unsigned long guest_es_base; + unsigned long guest_cs_base; + unsigned long guest_ss_base; + unsigned long guest_ds_base; + unsigned long guest_fs_base; + unsigned long guest_gs_base; + unsigned long guest_ldtr_base; + unsigned long guest_tr_base; + unsigned long guest_gdtr_base; + unsigned long guest_idtr_base; + unsigned long guest_dr7; + unsigned long guest_rsp; + unsigned long guest_rip; + unsigned long guest_rflags; + unsigned long guest_pending_dbg_exceptions; + unsigned long guest_sysenter_esp; + unsigned long guest_sysenter_eip; + unsigned long host_cr0; + unsigned long host_cr3; + unsigned long host_cr4; + unsigned long host_fs_base; + unsigned long host_gs_base; + unsigned long host_tr_base; + unsigned long host_gdtr_base; + unsigned long host_idtr_base; + unsigned long host_ia32_sysenter_esp; + unsigned long host_ia32_sysenter_eip; + unsigned long host_rsp; + unsigned long host_rip; +}; + #define VMCS12_REVISION 0x11e57ed0 /* @@ -139,6 +269,8 @@ struct __attribute__ ((__packed__)) vmcs u32 revision_id; u32 abort; + struct shadow_vmcs shadow_vmcs; + bool launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */ }; @@ -228,6 +360,169 @@ static inline struct vcpu_vmx *to_vmx(st return container_of(vcpu, struct vcpu_vmx, vcpu); } +#define OFFSET(x) offsetof(struct shadow_vmcs, x) + +static unsigned short vmcs_field_to_offset_table[HOST_RIP+1] = { + [VIRTUAL_PROCESSOR_ID] = OFFSET(virtual_processor_id), + [GUEST_ES_SELECTOR] = OFFSET(guest_es_selector), + [GUEST_CS_SELECTOR] = OFFSET(guest_cs_selector), + [GUEST_SS_SELECTOR] = OFFSET(guest_ss_selector), + [GUEST_DS_SELECTOR] = OFFSET(guest_ds_selector), + [GUEST_FS_SELECTOR] = OFFSET(guest_fs_selector), + [GUEST_GS_SELECTOR] = OFFSET(guest_gs_selector), + [GUEST_LDTR_SELECTOR] = OFFSET(guest_ldtr_selector), + [GUEST_TR_SELECTOR] = OFFSET(guest_tr_selector), + [HOST_ES_SELECTOR] = OFFSET(host_es_selector), + [HOST_CS_SELECTOR] = OFFSET(host_cs_selector), + [HOST_SS_SELECTOR] = OFFSET(host_ss_selector), + [HOST_DS_SELECTOR] = OFFSET(host_ds_selector), + [HOST_FS_SELECTOR] = OFFSET(host_fs_selector), + [HOST_GS_SELECTOR] = OFFSET(host_gs_selector), + [HOST_TR_SELECTOR] = OFFSET(host_tr_selector), + [IO_BITMAP_A] = OFFSET(io_bitmap_a), + [IO_BITMAP_A_HIGH] = OFFSET(io_bitmap_a)+4, + [IO_BITMAP_B] = OFFSET(io_bitmap_b), + [IO_BITMAP_B_HIGH] = OFFSET(io_bitmap_b)+4, + [MSR_BITMAP] = OFFSET(msr_bitmap), + [MSR_BITMAP_HIGH] = OFFSET(msr_bitmap)+4, + [VM_EXIT_MSR_STORE_ADDR] = OFFSET(vm_exit_msr_store_addr), + [VM_EXIT_MSR_STORE_ADDR_HIGH] = OFFSET(vm_exit_msr_store_addr)+4, + [VM_EXIT_MSR_LOAD_ADDR] = OFFSET(vm_exit_msr_load_addr), + [VM_EXIT_MSR_LOAD_ADDR_HIGH] = OFFSET(vm_exit_msr_load_addr)+4, + [VM_ENTRY_MSR_LOAD_ADDR] = OFFSET(vm_entry_msr_load_addr), + [VM_ENTRY_MSR_LOAD_ADDR_HIGH] = OFFSET(vm_entry_msr_load_addr)+4, + [TSC_OFFSET] = OFFSET(tsc_offset), + [TSC_OFFSET_HIGH] = OFFSET(tsc_offset)+4, + [VIRTUAL_APIC_PAGE_ADDR] = OFFSET(virtual_apic_page_addr), + [VIRTUAL_APIC_PAGE_ADDR_HIGH] = OFFSET(virtual_apic_page_addr)+4, + [APIC_ACCESS_ADDR] = OFFSET(apic_access_addr), + [APIC_ACCESS_ADDR_HIGH] = OFFSET(apic_access_addr)+4, + [EPT_POINTER] = OFFSET(ept_pointer), + [EPT_POINTER_HIGH] = OFFSET(ept_pointer)+4, + [GUEST_PHYSICAL_ADDRESS] = OFFSET(guest_physical_address), + [GUEST_PHYSICAL_ADDRESS_HIGH] = OFFSET(guest_physical_address)+4, + [VMCS_LINK_POINTER] = OFFSET(vmcs_link_pointer), + [VMCS_LINK_POINTER_HIGH] = OFFSET(vmcs_link_pointer)+4, + [GUEST_IA32_DEBUGCTL] = OFFSET(guest_ia32_debugctl), + [GUEST_IA32_DEBUGCTL_HIGH] = OFFSET(guest_ia32_debugctl)+4, + [GUEST_IA32_PAT] = OFFSET(guest_ia32_pat), + [GUEST_IA32_PAT_HIGH] = OFFSET(guest_ia32_pat)+4, + [GUEST_PDPTR0] = OFFSET(guest_pdptr0), + [GUEST_PDPTR0_HIGH] = OFFSET(guest_pdptr0)+4, + [GUEST_PDPTR1] = OFFSET(guest_pdptr1), + [GUEST_PDPTR1_HIGH] = OFFSET(guest_pdptr1)+4, + [GUEST_PDPTR2] = OFFSET(guest_pdptr2), + [GUEST_PDPTR2_HIGH] = OFFSET(guest_pdptr2)+4, + [GUEST_PDPTR3] = OFFSET(guest_pdptr3), + [GUEST_PDPTR3_HIGH] = OFFSET(guest_pdptr3)+4, + [HOST_IA32_PAT] = OFFSET(host_ia32_pat), + [HOST_IA32_PAT_HIGH] = OFFSET(host_ia32_pat)+4, + [PIN_BASED_VM_EXEC_CONTROL] = OFFSET(pin_based_vm_exec_control), + [CPU_BASED_VM_EXEC_CONTROL] = OFFSET(cpu_based_vm_exec_control), + [EXCEPTION_BITMAP] = OFFSET(exception_bitmap), + [PAGE_FAULT_ERROR_CODE_MASK] = OFFSET(page_fault_error_code_mask), + [PAGE_FAULT_ERROR_CODE_MATCH] = OFFSET(page_fault_error_code_match), + [CR3_TARGET_COUNT] = OFFSET(cr3_target_count), + [VM_EXIT_CONTROLS] = OFFSET(vm_exit_controls), + [VM_EXIT_MSR_STORE_COUNT] = OFFSET(vm_exit_msr_store_count), + [VM_EXIT_MSR_LOAD_COUNT] = OFFSET(vm_exit_msr_load_count), + [VM_ENTRY_CONTROLS] = OFFSET(vm_entry_controls), + [VM_ENTRY_MSR_LOAD_COUNT] = OFFSET(vm_entry_msr_load_count), + [VM_ENTRY_INTR_INFO_FIELD] = OFFSET(vm_entry_intr_info_field), + [VM_ENTRY_EXCEPTION_ERROR_CODE] = OFFSET(vm_entry_exception_error_code), + [VM_ENTRY_INSTRUCTION_LEN] = OFFSET(vm_entry_instruction_len), + [TPR_THRESHOLD] = OFFSET(tpr_threshold), + [SECONDARY_VM_EXEC_CONTROL] = OFFSET(secondary_vm_exec_control), + [VM_INSTRUCTION_ERROR] = OFFSET(vm_instruction_error), + [VM_EXIT_REASON] = OFFSET(vm_exit_reason), + [VM_EXIT_INTR_INFO] = OFFSET(vm_exit_intr_info), + [VM_EXIT_INTR_ERROR_CODE] = OFFSET(vm_exit_intr_error_code), + [IDT_VECTORING_INFO_FIELD] = OFFSET(idt_vectoring_info_field), + [IDT_VECTORING_ERROR_CODE] = OFFSET(idt_vectoring_error_code), + [VM_EXIT_INSTRUCTION_LEN] = OFFSET(vm_exit_instruction_len), + [VMX_INSTRUCTION_INFO] = OFFSET(vmx_instruction_info), + [GUEST_ES_LIMIT] = OFFSET(guest_es_limit), + [GUEST_CS_LIMIT] = OFFSET(guest_cs_limit), + [GUEST_SS_LIMIT] = OFFSET(guest_ss_limit), + [GUEST_DS_LIMIT] = OFFSET(guest_ds_limit), + [GUEST_FS_LIMIT] = OFFSET(guest_fs_limit), + [GUEST_GS_LIMIT] = OFFSET(guest_gs_limit), + [GUEST_LDTR_LIMIT] = OFFSET(guest_ldtr_limit), + [GUEST_TR_LIMIT] = OFFSET(guest_tr_limit), + [GUEST_GDTR_LIMIT] = OFFSET(guest_gdtr_limit), + [GUEST_IDTR_LIMIT] = OFFSET(guest_idtr_limit), + [GUEST_ES_AR_BYTES] = OFFSET(guest_es_ar_bytes), + [GUEST_CS_AR_BYTES] = OFFSET(guest_cs_ar_bytes), + [GUEST_SS_AR_BYTES] = OFFSET(guest_ss_ar_bytes), + [GUEST_DS_AR_BYTES] = OFFSET(guest_ds_ar_bytes), + [GUEST_FS_AR_BYTES] = OFFSET(guest_fs_ar_bytes), + [GUEST_GS_AR_BYTES] = OFFSET(guest_gs_ar_bytes), + [GUEST_LDTR_AR_BYTES] = OFFSET(guest_ldtr_ar_bytes), + [GUEST_TR_AR_BYTES] = OFFSET(guest_tr_ar_bytes), + [GUEST_INTERRUPTIBILITY_INFO] = OFFSET(guest_interruptibility_info), + [GUEST_ACTIVITY_STATE] = OFFSET(guest_activity_state), + [GUEST_SYSENTER_CS] = OFFSET(guest_sysenter_cs), + [HOST_IA32_SYSENTER_CS] = OFFSET(host_ia32_sysenter_cs), + [CR0_GUEST_HOST_MASK] = OFFSET(cr0_guest_host_mask), + [CR4_GUEST_HOST_MASK] = OFFSET(cr4_guest_host_mask), + [CR0_READ_SHADOW] = OFFSET(cr0_read_shadow), + [CR4_READ_SHADOW] = OFFSET(cr4_read_shadow), + [CR3_TARGET_VALUE0] = OFFSET(cr3_target_value0), + [CR3_TARGET_VALUE1] = OFFSET(cr3_target_value1), + [CR3_TARGET_VALUE2] = OFFSET(cr3_target_value2), + [CR3_TARGET_VALUE3] = OFFSET(cr3_target_value3), + [EXIT_QUALIFICATION] = OFFSET(exit_qualification), + [GUEST_LINEAR_ADDRESS] = OFFSET(guest_linear_address), + [GUEST_CR0] = OFFSET(guest_cr0), + [GUEST_CR3] = OFFSET(guest_cr3), + [GUEST_CR4] = OFFSET(guest_cr4), + [GUEST_ES_BASE] = OFFSET(guest_es_base), + [GUEST_CS_BASE] = OFFSET(guest_cs_base), + [GUEST_SS_BASE] = OFFSET(guest_ss_base), + [GUEST_DS_BASE] = OFFSET(guest_ds_base), + [GUEST_FS_BASE] = OFFSET(guest_fs_base), + [GUEST_GS_BASE] = OFFSET(guest_gs_base), + [GUEST_LDTR_BASE] = OFFSET(guest_ldtr_base), + [GUEST_TR_BASE] = OFFSET(guest_tr_base), + [GUEST_GDTR_BASE] = OFFSET(guest_gdtr_base), + [GUEST_IDTR_BASE] = OFFSET(guest_idtr_base), + [GUEST_DR7] = OFFSET(guest_dr7), + [GUEST_RSP] = OFFSET(guest_rsp), + [GUEST_RIP] = OFFSET(guest_rip), + [GUEST_RFLAGS] = OFFSET(guest_rflags), + [GUEST_PENDING_DBG_EXCEPTIONS] = OFFSET(guest_pending_dbg_exceptions), + [GUEST_SYSENTER_ESP] = OFFSET(guest_sysenter_esp), + [GUEST_SYSENTER_EIP] = OFFSET(guest_sysenter_eip), + [HOST_CR0] = OFFSET(host_cr0), + [HOST_CR3] = OFFSET(host_cr3), + [HOST_CR4] = OFFSET(host_cr4), + [HOST_FS_BASE] = OFFSET(host_fs_base), + [HOST_GS_BASE] = OFFSET(host_gs_base), + [HOST_TR_BASE] = OFFSET(host_tr_base), + [HOST_GDTR_BASE] = OFFSET(host_gdtr_base), + [HOST_IDTR_BASE] = OFFSET(host_idtr_base), + [HOST_IA32_SYSENTER_ESP] = OFFSET(host_ia32_sysenter_esp), + [HOST_IA32_SYSENTER_EIP] = OFFSET(host_ia32_sysenter_eip), + [HOST_RSP] = OFFSET(host_rsp), + [HOST_RIP] = OFFSET(host_rip), +}; + +static inline short vmcs_field_to_offset(unsigned long field) +{ + + if (field > HOST_RIP || vmcs_field_to_offset_table[field] == 0) { + printk(KERN_ERR "invalid vmcs field 0x%lx\n", field); + return -1; + } + return vmcs_field_to_offset_table[field]; +} + +static inline struct shadow_vmcs *get_shadow_vmcs(struct kvm_vcpu *vcpu) +{ + WARN_ON(!to_vmx(vcpu)->nested.current_l2_page); + return &(to_vmx(vcpu)->nested.current_l2_page->shadow_vmcs); +} + static struct page *nested_get_page(struct kvm_vcpu *vcpu, u64 vmcs_addr) { struct page *vmcs_page =