From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=55034 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OWK4D-0003MC-CB for qemu-devel@nongnu.org; Tue, 06 Jul 2010 22:08:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OWK4C-0006mN-5K for qemu-devel@nongnu.org; Tue, 06 Jul 2010 22:08:53 -0400 Received: from mail.valinux.co.jp ([210.128.90.3]:54710) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OWK4B-0006lo-RY for qemu-devel@nongnu.org; Tue, 06 Jul 2010 22:08:52 -0400 Date: Wed, 7 Jul 2010 11:04:51 +0900 From: Isaku Yamahata Message-ID: <20100707020451.GA30653@valinux.co.jp> References: <20100706112327.GA20108@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100706112327.GA20108@redhat.com> Subject: [Qemu-devel] Re: [PATCH] pci: pass bridge update to secondary bus List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: qemu-devel@nongnu.org On Tue, Jul 06, 2010 at 02:23:27PM +0300, Michael S. Tsirkin wrote: > bridge config write should trigger updates > on the secondary bus. never on the primary bus. > > Signed-off-by: Michael S. Tsirkin > --- > > Compile-tested only. > Isaku Yamahata, could you review this please? > You wrote the code, and you seem to have some bridged setups. The code looks good. Should PCIBridge::bus be renamed to something like PCIBridge::secondary_bus (or sec_bus for short) in order to avoid confusion? The redundant local variable, secondary_bus, was deliberately introduced to emphasize that it's a secondary bus. And I was confused by that. Anyway such a change should be done by another patch. > > hw/pci.c | 4 +++- > 1 files changed, 3 insertions(+), 1 deletions(-) > > diff --git a/hw/pci.c b/hw/pci.c > index 926cf63..011d83e 100644 > --- a/hw/pci.c > +++ b/hw/pci.c > @@ -1513,7 +1513,9 @@ static void pci_bridge_write_config(PCIDevice *d, > /* memory base/limit, prefetchable base/limit and > io base/limit upper 16 */ > ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) { > - pci_bridge_update_mappings(d->bus); > + PCIBridge *s = container_of(d, PCIBridge, dev); > + PCIBus *secondary_bus = &s->bus; > + pci_bridge_update_mappings(secondary_bus); > } > } > > -- > 1.7.2.rc0.14.g41c1c > -- yamahata