From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH] drm/i915: Fix offset page-flips on i965+
Date: Sun, 8 Aug 2010 16:50:08 +0200
Message-ID: <20100808145008.GB15846@viiv.ffwll.ch>
References: <4C5E04F9.5010005@comcast.net>
	<1281259225-23421-1-git-send-email-chris@chris-wilson.co.uk>
	<89k83a$974h4e@azsmga001.ch.intel.com>
	<20100808122410.GA15846@viiv.ffwll.ch>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Return-path: <intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org>
Received: from mail.ffwll.ch (cable-static-49-187.intergga.ch [157.161.49.187])
	by gabe.freedesktop.org (Postfix) with ESMTP id A37A39E8FB
	for <intel-gfx@lists.freedesktop.org>;
	Sun,  8 Aug 2010 07:48:20 -0700 (PDT)
Content-Disposition: inline
In-Reply-To: <20100808122410.GA15846@viiv.ffwll.ch>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
List-Id: intel-gfx@lists.freedesktop.org

On Sun, Aug 08, 2010 at 02:24:11PM +0200, Daniel Vetter wrote:
> In conclusion I think we need an if (IS_SNB(dev)) that sets dword 0, bit
> 22 to 1 and ensures that dword 2, bit 0 is zero. For the rest of of the
> IS_I965G branch we might as well write 0 instead of pitch and tiling_mode.

I've played around a bit and it looks like everyone is wrong (minus the
current code;). Tested on my ilk (thinkpad t410) ymmv.

Not setting pitch or tiling_mode is a bad idea and results in garbage on
the screen. So hw does indeed read this values (despite what the docs seem
to claim). But at least for my ilk here, published docs are correct: Or'ing
it in with the pitch results in garbage, too.

The original patch is therefore broken, 'cause it moves around the
tiling_mode bit (with mentioning this in the changelog).

I suspect something changed with sandybridge and whoever wrote the docs
made a mess out of it.

-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48