From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tony Lindgren Subject: Re: [PATCH 5/6] ARM: Don't set TLB ops broadcasting on UP ARMv7 Date: Thu, 2 Sep 2010 10:21:33 -0700 Message-ID: <20100902172133.GT11597@atomide.com> References: <20100819073810.GR12184@atomide.com> <4C6CFBAF.6020407@canonical.com> <20100819095705.GU12184@atomide.com> <20100819102025.GA32151@n2100.arm.linux.org.uk> <20100820120622.GL25742@atomide.com> <20100830225527.GC11597@atomide.com> <20100902133637.GJ26319@n2100.arm.linux.org.uk> <20100902161659.GJ11597@atomide.com> <20100902162220.GO11597@atomide.com> <20100902165756.GV26319@n2100.arm.linux.org.uk> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Received: from mho-02-ewr.mailhop.org ([204.13.248.72]:51606 "EHLO mho-02-ewr.mailhop.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752167Ab0IBRVp (ORCPT ); Thu, 2 Sep 2010 13:21:45 -0400 Content-Disposition: inline In-Reply-To: <20100902165756.GV26319@n2100.arm.linux.org.uk> Sender: linux-omap-owner@vger.kernel.org List-Id: linux-omap@vger.kernel.org To: Russell King - ARM Linux Cc: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bryan Wu , Will Deacon * Russell King - ARM Linux [100902 09:50]: > On Thu, Sep 02, 2010 at 09:22:20AM -0700, Tony Lindgren wrote: > > >From 8b22546af2ba9a0d96c2f419bfcec1f3c01a414d Mon Sep 17 00:00:00 2001 > > From: Tony Lindgren > > Date: Mon, 30 Aug 2010 14:03:28 -0700 > > Subject: [PATCH 5/6] ARM: Don't set TLB ops broadcasting on UP ARMv7 > > > > Don't set TLB ops broadcasting on UP ARMv7. Looks like these bits > > are also different on A8 and A9. > > This is already taken care of. > > > diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S > > index 07fc660..51a063d 100644 > > --- a/arch/arm/mm/proc-v7.S > > +++ b/arch/arm/mm/proc-v7.S > > @@ -191,7 +191,8 @@ __v7_setup: > > UP(mov r0, #(1 << 6)) @ fake it for UP > > If it's UP, we set r0 to 1 << 6, which... > > > tst r0, #(1 << 6) @ SMP/nAMP mode enabled? > > means this test produces a non-zero result. > > > orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and > > - mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting > > And therefore these instructions will not be executed. AFAIK these bits are different for Cortex-A8 and A9, bit 6 is IBE on A8. Tony From mboxrd@z Thu Jan 1 00:00:00 1970 From: tony@atomide.com (Tony Lindgren) Date: Thu, 2 Sep 2010 10:21:33 -0700 Subject: [PATCH 5/6] ARM: Don't set TLB ops broadcasting on UP ARMv7 In-Reply-To: <20100902165756.GV26319@n2100.arm.linux.org.uk> References: <20100819073810.GR12184@atomide.com> <4C6CFBAF.6020407@canonical.com> <20100819095705.GU12184@atomide.com> <20100819102025.GA32151@n2100.arm.linux.org.uk> <20100820120622.GL25742@atomide.com> <20100830225527.GC11597@atomide.com> <20100902133637.GJ26319@n2100.arm.linux.org.uk> <20100902161659.GJ11597@atomide.com> <20100902162220.GO11597@atomide.com> <20100902165756.GV26319@n2100.arm.linux.org.uk> Message-ID: <20100902172133.GT11597@atomide.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org * Russell King - ARM Linux [100902 09:50]: > On Thu, Sep 02, 2010 at 09:22:20AM -0700, Tony Lindgren wrote: > > >From 8b22546af2ba9a0d96c2f419bfcec1f3c01a414d Mon Sep 17 00:00:00 2001 > > From: Tony Lindgren > > Date: Mon, 30 Aug 2010 14:03:28 -0700 > > Subject: [PATCH 5/6] ARM: Don't set TLB ops broadcasting on UP ARMv7 > > > > Don't set TLB ops broadcasting on UP ARMv7. Looks like these bits > > are also different on A8 and A9. > > This is already taken care of. > > > diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S > > index 07fc660..51a063d 100644 > > --- a/arch/arm/mm/proc-v7.S > > +++ b/arch/arm/mm/proc-v7.S > > @@ -191,7 +191,8 @@ __v7_setup: > > UP(mov r0, #(1 << 6)) @ fake it for UP > > If it's UP, we set r0 to 1 << 6, which... > > > tst r0, #(1 << 6) @ SMP/nAMP mode enabled? > > means this test produces a non-zero result. > > > orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and > > - mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting > > And therefore these instructions will not be executed. AFAIK these bits are different for Cortex-A8 and A9, bit 6 is IBE on A8. Tony