From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from [140.186.70.92] (port=46839 helo=eggs.gnu.org)
	by lists.gnu.org with esmtp (Exim 4.43) id 1OuKFt-0005zQ-SD
	for qemu-devel@nongnu.org; Sat, 11 Sep 2010 03:12:10 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69)
	(envelope-from <edgar.iglesias@gmail.com>) id 1OuKFs-0005eo-Vl
	for qemu-devel@nongnu.org; Sat, 11 Sep 2010 03:12:09 -0400
Received: from mail-ey0-f173.google.com ([209.85.215.173]:38338)
	by eggs.gnu.org with esmtp (Exim 4.69)
	(envelope-from <edgar.iglesias@gmail.com>) id 1OuKFs-0005eh-RW
	for qemu-devel@nongnu.org; Sat, 11 Sep 2010 03:12:08 -0400
Received: by eyf18 with SMTP id 18so2461081eyf.4
	for <qemu-devel@nongnu.org>; Sat, 11 Sep 2010 00:12:07 -0700 (PDT)
Date: Sat, 11 Sep 2010 09:12:03 +0200
From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Message-ID: <20100911071203.GA25515@laped.lan>
References: <1284167314-11594-1-git-send-email-agraf@suse.de>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <1284167314-11594-1-git-send-email-agraf@suse.de>
Subject: [Qemu-devel] Re: [PATCH 0/2] PowerPC fixes
List-Id: qemu-devel.nongnu.org
List-Unsubscribe: <http://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <http://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Alexander Graf <agraf@suse.de>
Cc: Thomas Monjalon <thomas@monjalon.net>, QEMU Developers <qemu-devel@nongnu.org>

On Sat, Sep 11, 2010 at 03:08:32AM +0200, Alexander Graf wrote:
> There goes another round of PowerPC fixes. Originally this should only have
> been a fix for the MSR_POW issue (bug 608107), but I also stumbed over recent
> Linux kernels not booting in qemu-system-ppc64. So a fix for that is also
> included.
> 
> With this new logic I didn't really took care of all HV corner cases, but HV
> mode is not properly implemented anyways (read: we should probably rip it out
> or do it properly, whichever is easier). I'm also fairly sure that the way
> things are now BookE doesn't work at all, so things again haven't become worse.
>
> Alexander Graf (2):
>   PPC: Enable hint bits for lwarx/ldarx
>   PPC: Redesign interrupt trigger path


FWIW the MSR parts look good to me.
Also, none of this seems to break anything on my Virtex5 PPC-440 BookE
board (Im working on cleaning that up so it eventually can be submitted).

Cheers

Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>