From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=46425 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PJPdt-00048u-Ob for qemu-devel@nongnu.org; Fri, 19 Nov 2010 07:00:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PJPdh-0002qp-Ld for qemu-devel@nongnu.org; Fri, 19 Nov 2010 07:00:37 -0500 Received: from mx1.redhat.com ([209.132.183.28]:16143) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PJPdh-0002qa-DS for qemu-devel@nongnu.org; Fri, 19 Nov 2010 07:00:25 -0500 Date: Fri, 19 Nov 2010 14:00:13 +0200 From: "Michael S. Tsirkin" Message-ID: <20101119120012.GA5713@redhat.com> References: <2a4a27e9b27f0e75052fc52f36449e397fd5a65d.1290160397.git.yamahata@valinux.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <2a4a27e9b27f0e75052fc52f36449e397fd5a65d.1290160397.git.yamahata@valinux.co.jp> Subject: [Qemu-devel] Re: [PATCH v2 6/6] pci bridge: implement secondary bus reset List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Isaku Yamahata Cc: skandasa@cisco.com, Anthony Liguori , etmartin@cisco.com, wexu2@cisco.com, qemu-devel@nongnu.org, pbonzini@redhat.com On Fri, Nov 19, 2010 at 06:56:03PM +0900, Isaku Yamahata wrote: > Emulates secondary bus reset when secondary bus reset bit > is written from 0 to 1. > Interesting. This is not exactly what happens on real hardware though: there, RST# stays asserted until bit is cleared. So for example attempts to scan the secondary bus will return nothing. Can implement this later, but please add a comment here. > Signed-off-by: Isaku Yamahata > Signed-off-by: Anthony Liguori > --- > hw/pci_bridge.c | 12 +++++++++++- > 1 files changed, 11 insertions(+), 1 deletions(-) > > diff --git a/hw/pci_bridge.c b/hw/pci_bridge.c > index 58cc2e4..618a81e 100644 > --- a/hw/pci_bridge.c > +++ b/hw/pci_bridge.c > @@ -139,6 +139,10 @@ pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type) > void pci_bridge_write_config(PCIDevice *d, > uint32_t address, uint32_t val, int len) > { > + PCIBridge *s = container_of(d, PCIBridge, dev); > + uint16_t bridge_control = pci_get_word(d->config + PCI_BRIDGE_CONTROL); > + uint16_t bridge_control_new; I'd prefer shorter names for local variables. > + > pci_default_write_config(d, address, val, len); > > if (/* io base/limit */ > @@ -147,9 +151,15 @@ void pci_bridge_write_config(PCIDevice *d, > /* memory base/limit, prefetchable base/limit and > io base/limit upper 16 */ > ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) { > - PCIBridge *s = container_of(d, PCIBridge, dev); > pci_bridge_update_mappings(&s->sec_bus); > } > + > + bridge_control_new = pci_get_word(d->config + PCI_BRIDGE_CONTROL); > + if (!(bridge_control & PCI_BRIDGE_CTL_BUS_RESET) && > + (bridge_control_new & PCI_BRIDGE_CTL_BUS_RESET)) { Equivalent but shorter: ~bridge_control & bridge_control_new & PCI_BRIDGE_CTL_BUS_RESET > + /* 0 -> 1 */ > + pci_bus_reset(&s->sec_bus); > + } > } > > void pci_bridge_disable_base_limit(PCIDevice *dev) > -- > 1.7.1.1