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Date: Mon, 22 Nov 2010 12:54:44 +0200
From: "Michael S. Tsirkin" <mst@redhat.com>
Message-ID: <20101122105444.GA25877@redhat.com>
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Subject: [Qemu-devel] Re: [PATCH v2 0/6] qdev reset refactoring and pci bus
	reset
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To: Isaku Yamahata <yamahata@valinux.co.jp>
Cc: skandasa@cisco.com, etmartin@cisco.com, wexu2@cisco.com, qemu-devel@nongnu.org, kraxel@redhat.com, pbonzini@redhat.com

On Mon, Nov 22, 2010 at 07:43:37PM +0900, Isaku Yamahata wrote:
> On Mon, Nov 22, 2010 at 09:54:02AM +0200, Michael S. Tsirkin wrote:
> > On Fri, Nov 19, 2010 at 06:55:57PM +0900, Isaku Yamahata wrote:
> > > Here is v2. I updated the comments, and dropped the pci qdev reset patch.
> > > 
> > > Patch description:
> > > The goal of this patch series is to implement secondary bus reset
> > > emulation in pci-to-pci bridge.
> > > At first, this patch series refactors qdev reset,
> > > and then cleans up pci bus reset. Lastly implements pci bridge control
> > > secondary bus reset bit.
> > > 
> > > This patch series is for pci bus reset, which is ported
> > > from the following repo.
> > > git://repo.or.cz/qemu/aliguori.git qdev-refactor
> > 
> > I've put the series on my pci branch, tweaking patches 5 and 6 in the
> > process.  Out of time to compile-tested only for now.
> 
> Thank you. The tweaking looks good.
> Do you still want me to send another patch to add a comment on RST#?

Probably not. I'm not sure I understand what the conventional
PCI spec says: should devices be reset on 0->1
transition, or kept in reset state until this bit is cleared?
And it seems quite clear that in the express
case the reset is only for 0->1 transition.
I've asked for clarification from pcisig.

> -- 
> yamahata