From mboxrd@z Thu Jan  1 00:00:00 1970
From: Christoph Egger <Christoph.Egger@amd.com>
Subject: Re: [PATCH 05/13] Nested Virtualization: CRn & paged real
	mode
Date: Thu, 2 Dec 2010 18:42:04 +0100
Message-ID: <201012021842.05100.Christoph.Egger@amd.com>
References: <201011121942.15267.Christoph.Egger@amd.com>
	<20101116131914.GB25462@whitby.uk.xensource.com>
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To: Tim Deegan <Tim.Deegan@citrix.com>
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On Tuesday 16 November 2010 14:19:14 Tim Deegan wrote:
> At 18:42 +0000 on 12 Nov (1289587334), Christoph Egger wrote:
> > @@ -1096,7 +1097,8 @@ int hvm_set_cr0(unsigned long value)
> >      /* ET is reserved and should be always be 1. */
> >      value |= X86_CR0_ET;
> >
> > -    if ( (value & (X86_CR0_PE | X86_CR0_PG)) == X86_CR0_PG )
> > +    if ( !nestedhvm_vmswitch_in_progress(v) &&
> > +         (value & (X86_CR0_PE | X86_CR0_PG)) == X86_CR0_PG )
> >          goto gpf;
> >
> >      if ( (value & X86_CR0_PG) && !(old_value & X86_CR0_PG) )
> > @@ -1150,7 +1152,7 @@ int hvm_set_cr0(unsigned long value)
> >          }
> >      }
> >
> > -    if ( has_arch_mmios(v->domain) )
> > +    if ( !nestedhvm_vmswitch_in_progress(v) && has_arch_mmios(v->domain)
> > ) {
> >          if ( (value & X86_CR0_CD) && !(value & X86_CR0_NW) )
> >          {
>
> Like I said last time:
>
> I don't think that needs to happen -- it's up to the L1 VMM to decide
> whether the L2 VMM should be allowed to set cache control bits in CR0.

I think, I misunderstood you then. Fixed in local tree.

Christoph


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