From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757883Ab1ANPtl (ORCPT ); Fri, 14 Jan 2011 10:49:41 -0500 Received: from caramon.arm.linux.org.uk ([78.32.30.218]:34039 "EHLO caramon.arm.linux.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757687Ab1ANPtf (ORCPT ); Fri, 14 Jan 2011 10:49:35 -0500 Date: Fri, 14 Jan 2011 15:49:19 +0000 From: Russell King - ARM Linux To: Catalin Marinas Cc: Colin Cross , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] ARM: vfp: Fix up exception location in Thumb mode Message-ID: <20110114154919.GE15996@n2100.arm.linux.org.uk> References: <1294990949-2729-1-git-send-email-ccross@android.com> <20110114120229.GA15996@n2100.arm.linux.org.uk> <1295014231.7901.41.camel@e102109-lin.cambridge.arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1295014231.7901.41.camel@e102109-lin.cambridge.arm.com> User-Agent: Mutt/1.5.19 (2009-01-05) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jan 14, 2011 at 02:10:31PM +0000, Catalin Marinas wrote: > On Fri, 2011-01-14 at 12:02 +0000, Russell King - ARM Linux wrote: > > I don't think this is correct. On entry to the undefined instruction > > handler, we get the uncorrected PC value, so PC points to the > > instruction after the faulting instruction. > > > > If it was an ARM instruction, that is located at PC-4. If it was a > > Thumb instruction, it is located at PC-2. This PC value is passed > > unmodified to the VFP entry code, and the passed r2 reflect the > > value in regs->ARM_pc. > > The entry-armv.S code adds 2 to the r2 register in case of a 32-bit > Thumb instruction, so it is no longer the same as the ARM_pc. That's something that should be fixed - the entry conditions should be the same irrespective of thumb or arm encoding. > Since the VFP instructions in Thumb mode are always 32-bit, Colin's > patch made sense to me. I looked up the VADD instruction in the ARM ARM. It has both a 16-bit and 32-bit encoding. > > I think that the undefined instruction handling needs reworking for > > Thumb entirely as we could be dealing with a 16-bit or 32-bit thumb > > instruction, and we have no way of knowing without repeatedly > > decoding that instruction. > > We already handle the r2 for in __und_usr. We don't deal with ARM_pc but > we could either do it in __und_usr or let the code handling the undef > fix it up. At the moment its just confusing as things stand, as some things are changed in one place and not the other. Let's kill the pointless addition of 2 in the undefined instruction handler so that in every case we enter handlers with r2 == regs->ARM_pc, and regs->ARM_pc as per the ARM ARM undefined exception entry LR. Undefined instruction exception handlers can then rely on the meaning of both of these. From mboxrd@z Thu Jan 1 00:00:00 1970 From: linux@arm.linux.org.uk (Russell King - ARM Linux) Date: Fri, 14 Jan 2011 15:49:19 +0000 Subject: [PATCH] ARM: vfp: Fix up exception location in Thumb mode In-Reply-To: <1295014231.7901.41.camel@e102109-lin.cambridge.arm.com> References: <1294990949-2729-1-git-send-email-ccross@android.com> <20110114120229.GA15996@n2100.arm.linux.org.uk> <1295014231.7901.41.camel@e102109-lin.cambridge.arm.com> Message-ID: <20110114154919.GE15996@n2100.arm.linux.org.uk> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, Jan 14, 2011 at 02:10:31PM +0000, Catalin Marinas wrote: > On Fri, 2011-01-14 at 12:02 +0000, Russell King - ARM Linux wrote: > > I don't think this is correct. On entry to the undefined instruction > > handler, we get the uncorrected PC value, so PC points to the > > instruction after the faulting instruction. > > > > If it was an ARM instruction, that is located at PC-4. If it was a > > Thumb instruction, it is located at PC-2. This PC value is passed > > unmodified to the VFP entry code, and the passed r2 reflect the > > value in regs->ARM_pc. > > The entry-armv.S code adds 2 to the r2 register in case of a 32-bit > Thumb instruction, so it is no longer the same as the ARM_pc. That's something that should be fixed - the entry conditions should be the same irrespective of thumb or arm encoding. > Since the VFP instructions in Thumb mode are always 32-bit, Colin's > patch made sense to me. I looked up the VADD instruction in the ARM ARM. It has both a 16-bit and 32-bit encoding. > > I think that the undefined instruction handling needs reworking for > > Thumb entirely as we could be dealing with a 16-bit or 32-bit thumb > > instruction, and we have no way of knowing without repeatedly > > decoding that instruction. > > We already handle the r2 for in __und_usr. We don't deal with ARM_pc but > we could either do it in __und_usr or let the code handling the undef > fix it up. At the moment its just confusing as things stand, as some things are changed in one place and not the other. Let's kill the pointless addition of 2 in the undefined instruction handler so that in every case we enter handlers with r2 == regs->ARM_pc, and regs->ARM_pc as per the ARM ARM undefined exception entry LR. Undefined instruction exception handlers can then rely on the meaning of both of these.