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diff for duplicates of <20110123154607.GC30094@n2100.arm.linux.org.uk>

diff --git a/a/1.txt b/N1/1.txt
index 1423366..0e24ac1 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -4,29 +4,29 @@ On Sun, Jan 16, 2011 at 09:25:00PM +0000, Catalin Marinas wrote:
 > > On Sat, Jan 15, 2011 at 03:31:04PM +0000, Catalin Marinas wrote:
 > >> On 14 January 2011 17:30, Russell King - ARM Linux
 > >> <linux@arm.linux.org.uk> wrote:
-> >> > +@  r9  = normal "successful" return address
-> >> >  @  r10 = vfp_state union
-> >> >  @  r11 = CPU number
-> >> > -@  lr  = failure return
+> >> > +@ ?r9 ?= normal "successful" return address
+> >> > ?@ ?r10 = vfp_state union
+> >> > ?@ ?r11 = CPU number
+> >> > -@ ?lr ?= failure return
 > >> > -
-> >> > +@  lr  = unrecognised instruction return address
-> >> > +@  IRQs enabled.
-> >> >  ENTRY(vfp_support_entry)
-> >> >        DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10
+> >> > +@ ?lr ?= unrecognised instruction return address
+> >> > +@ ?IRQs enabled.
+> >> > ?ENTRY(vfp_support_entry)
+> >> > ? ? ? ?DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10
 > >> >
 > >> > @@ -138,9 +138,12 @@ check_for_exception:
-> >> >                                        @ exception before retrying branch
-> >> >                                        @ out before setting an FPEXC that
-> >> >                                        @ stops us reading stuff
-> >> > -       VFPFMXR FPEXC, r1               @ restore FPEXC last
-> >> > -       sub     r2, r2, #4
-> >> > -       str     r2, [sp, #S_PC]         @ retry the instruction
-> >> > +       VFPFMXR FPEXC, r1               @ Restore FPEXC last
-> >> > +       sub     r2, r2, #4              @ Retry current instruction - if Thumb
-> >> > +       str     r2, [sp, #S_PC]         @ mode it's two 16-bit instructions,
-> >> > +                                       @ else it's one 32-bit instruction, so
-> >> > +                                       @ always subtract 4 from the following
-> >> > +                                       @ instruction address.
+> >> > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?@ exception before retrying branch
+> >> > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?@ out before setting an FPEXC that
+> >> > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?@ stops us reading stuff
+> >> > - ? ? ? VFPFMXR FPEXC, r1 ? ? ? ? ? ? ? @ restore FPEXC last
+> >> > - ? ? ? sub ? ? r2, r2, #4
+> >> > - ? ? ? str ? ? r2, [sp, #S_PC] ? ? ? ? @ retry the instruction
+> >> > + ? ? ? VFPFMXR FPEXC, r1 ? ? ? ? ? ? ? @ Restore FPEXC last
+> >> > + ? ? ? sub ? ? r2, r2, #4 ? ? ? ? ? ? ?@ Retry current instruction - if Thumb
+> >> > + ? ? ? str ? ? r2, [sp, #S_PC] ? ? ? ? @ mode it's two 16-bit instructions,
+> >> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? @ else it's one 32-bit instruction, so
+> >> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? @ always subtract 4 from the following
+> >> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? @ instruction address.
 > >>
 > >> I would say it's always a 32-bit instruction but made up of two 16-bit
 > >> values to allow half-word alignment.
diff --git a/a/content_digest b/N1/content_digest
index 2b492a4..93df39a 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -29,21 +29,16 @@
   "ref\0AANLkTim8OhAtqADck0Snq-7z7opw=coiQ4=DeO0O7Qa-\@mail.gmail.com\0"
 ]
 [
-  "From\0Russell King - ARM Linux <linux\@arm.linux.org.uk>\0"
+  "From\0linux\@arm.linux.org.uk (Russell King - ARM Linux)\0"
 ]
 [
-  "Subject\0Re: [PATCH] ARM: vfp: Fix up exception location in Thumb mode\0"
+  "Subject\0[PATCH] ARM: vfp: Fix up exception location in Thumb mode\0"
 ]
 [
   "Date\0Sun, 23 Jan 2011 15:46:07 +0000\0"
 ]
 [
-  "To\0Catalin Marinas <catalin.marinas\@arm.com>\0"
-]
-[
-  "Cc\0Colin Cross <ccross\@android.com>",
-  " linux-arm-kernel\@lists.infradead.org",
-  " linux-kernel\@vger.kernel.org\0"
+  "To\0linux-arm-kernel\@lists.infradead.org\0"
 ]
 [
   "\0000:1\0"
@@ -58,29 +53,29 @@
   "> > On Sat, Jan 15, 2011 at 03:31:04PM +0000, Catalin Marinas wrote:\n",
   "> >> On 14 January 2011 17:30, Russell King - ARM Linux\n",
   "> >> <linux\@arm.linux.org.uk> wrote:\n",
-  "> >> > +\@ \302\240r9 \302\240= normal \"successful\" return address\n",
-  "> >> > \302\240\@ \302\240r10 = vfp_state union\n",
-  "> >> > \302\240\@ \302\240r11 = CPU number\n",
-  "> >> > -\@ \302\240lr \302\240= failure return\n",
+  "> >> > +\@ ?r9 ?= normal \"successful\" return address\n",
+  "> >> > ?\@ ?r10 = vfp_state union\n",
+  "> >> > ?\@ ?r11 = CPU number\n",
+  "> >> > -\@ ?lr ?= failure return\n",
   "> >> > -\n",
-  "> >> > +\@ \302\240lr \302\240= unrecognised instruction return address\n",
-  "> >> > +\@ \302\240IRQs enabled.\n",
-  "> >> > \302\240ENTRY(vfp_support_entry)\n",
-  "> >> > \302\240 \302\240 \302\240 \302\240DBGSTR3 \"instr %08x pc %08x state %p\", r0, r2, r10\n",
+  "> >> > +\@ ?lr ?= unrecognised instruction return address\n",
+  "> >> > +\@ ?IRQs enabled.\n",
+  "> >> > ?ENTRY(vfp_support_entry)\n",
+  "> >> > ? ? ? ?DBGSTR3 \"instr %08x pc %08x state %p\", r0, r2, r10\n",
   "> >> >\n",
   "> >> > \@\@ -138,9 +138,12 \@\@ check_for_exception:\n",
-  "> >> > \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240\@ exception before retrying branch\n",
-  "> >> > \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240\@ out before setting an FPEXC that\n",
-  "> >> > \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240\@ stops us reading stuff\n",
-  "> >> > - \302\240 \302\240 \302\240 VFPFMXR FPEXC, r1 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \@ restore FPEXC last\n",
-  "> >> > - \302\240 \302\240 \302\240 sub \302\240 \302\240 r2, r2, #4\n",
-  "> >> > - \302\240 \302\240 \302\240 str \302\240 \302\240 r2, [sp, #S_PC] \302\240 \302\240 \302\240 \302\240 \@ retry the instruction\n",
-  "> >> > + \302\240 \302\240 \302\240 VFPFMXR FPEXC, r1 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \@ Restore FPEXC last\n",
-  "> >> > + \302\240 \302\240 \302\240 sub \302\240 \302\240 r2, r2, #4 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240\@ Retry current instruction - if Thumb\n",
-  "> >> > + \302\240 \302\240 \302\240 str \302\240 \302\240 r2, [sp, #S_PC] \302\240 \302\240 \302\240 \302\240 \@ mode it's two 16-bit instructions,\n",
-  "> >> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \@ else it's one 32-bit instruction, so\n",
-  "> >> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \@ always subtract 4 from the following\n",
-  "> >> > + \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \@ instruction address.\n",
+  "> >> > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\@ exception before retrying branch\n",
+  "> >> > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\@ out before setting an FPEXC that\n",
+  "> >> > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\@ stops us reading stuff\n",
+  "> >> > - ? ? ? VFPFMXR FPEXC, r1 ? ? ? ? ? ? ? \@ restore FPEXC last\n",
+  "> >> > - ? ? ? sub ? ? r2, r2, #4\n",
+  "> >> > - ? ? ? str ? ? r2, [sp, #S_PC] ? ? ? ? \@ retry the instruction\n",
+  "> >> > + ? ? ? VFPFMXR FPEXC, r1 ? ? ? ? ? ? ? \@ Restore FPEXC last\n",
+  "> >> > + ? ? ? sub ? ? r2, r2, #4 ? ? ? ? ? ? ?\@ Retry current instruction - if Thumb\n",
+  "> >> > + ? ? ? str ? ? r2, [sp, #S_PC] ? ? ? ? \@ mode it's two 16-bit instructions,\n",
+  "> >> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \@ else it's one 32-bit instruction, so\n",
+  "> >> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \@ always subtract 4 from the following\n",
+  "> >> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \@ instruction address.\n",
   "> >>\n",
   "> >> I would say it's always a 32-bit instruction but made up of two 16-bit\n",
   "> >> values to allow half-word alignment.\n",
@@ -272,4 +267,4 @@
   " \tldr\tr4, [r10, #TI_PREEMPT]\t\@ get preempt count"
 ]
 
-56f440c91d85dbb0986e51e37a053bf1b38388c6f7d9778b9a06cbce01b03989
+0f26ba146a6708e37c330b62aed1bf03ab8fcbcba35facc82cb2db1e1224ffbd
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