From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751324Ab1AWPwN (ORCPT ); Sun, 23 Jan 2011 10:52:13 -0500 Received: from caramon.arm.linux.org.uk ([78.32.30.218]:50807 "EHLO caramon.arm.linux.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751197Ab1AWPwM (ORCPT ); Sun, 23 Jan 2011 10:52:12 -0500 Date: Sun, 23 Jan 2011 15:51:57 +0000 From: Russell King - ARM Linux To: Catalin Marinas Cc: Colin Cross , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH] ARM: vfp: Fix up exception location in Thumb mode Message-ID: <20110123155157.GD30094@n2100.arm.linux.org.uk> References: <20110114120229.GA15996@n2100.arm.linux.org.uk> <1295014231.7901.41.camel@e102109-lin.cambridge.arm.com> <20110114154919.GE15996@n2100.arm.linux.org.uk> <1295022193.7901.56.camel@e102109-lin.cambridge.arm.com> <20110114163520.GH15996@n2100.arm.linux.org.uk> <1295024327.7901.70.camel@e102109-lin.cambridge.arm.com> <20110114173050.GJ15996@n2100.arm.linux.org.uk> <20110115154019.GF15996@n2100.arm.linux.org.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.5.19 (2009-01-05) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Jan 16, 2011 at 11:49:21AM +0000, Catalin Marinas wrote: > On Saturday, 15 January 2011, Russell King - ARM Linux > wrote: > > It's a reveq, so I thought we should cover all the instructions with > > an 'eq' conditional for thumb. > > If the it instruction doesn't cover all instructions, gas generates > some more its. But in this case, for little endian, the it instruction > covers more since reveq isn't included and having the beq not last in > the block I think is unpredictable. If you really want to optimise the > big endian case not to have an additional it generated by gas, you can > write ittt so that beq is included with little endian but not with big > endian. I wouldn't bother much for an extra it anyway. I think the itttt is correct. Unless you wish to illustrate why you think it's wrong by pasting the code and showing why you think the beq isn't the last instruction... > >         tst     r3, #PSR_T_BIT > >         subeq   r4, r2, #4 > > 1:      ldreqt  r0, [r4] > >         reveq   r0, r0 > >         beq     call_fpe > > You can have the T bit set but the instruction a 32-bit Thumb in which > case r2 is in the middle of such instruction rather than the next. > Unless you only refer to the ARM mode, in which case the comment is > fine. So? I'm confused why you're making a mountain out of apparantly nothing. From mboxrd@z Thu Jan 1 00:00:00 1970 From: linux@arm.linux.org.uk (Russell King - ARM Linux) Date: Sun, 23 Jan 2011 15:51:57 +0000 Subject: [PATCH] ARM: vfp: Fix up exception location in Thumb mode In-Reply-To: References: <20110114120229.GA15996@n2100.arm.linux.org.uk> <1295014231.7901.41.camel@e102109-lin.cambridge.arm.com> <20110114154919.GE15996@n2100.arm.linux.org.uk> <1295022193.7901.56.camel@e102109-lin.cambridge.arm.com> <20110114163520.GH15996@n2100.arm.linux.org.uk> <1295024327.7901.70.camel@e102109-lin.cambridge.arm.com> <20110114173050.GJ15996@n2100.arm.linux.org.uk> <20110115154019.GF15996@n2100.arm.linux.org.uk> Message-ID: <20110123155157.GD30094@n2100.arm.linux.org.uk> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Sun, Jan 16, 2011 at 11:49:21AM +0000, Catalin Marinas wrote: > On Saturday, 15 January 2011, Russell King - ARM Linux > wrote: > > It's a reveq, so I thought we should cover all the instructions with > > an 'eq' conditional for thumb. > > If the it instruction doesn't cover all instructions, gas generates > some more its. But in this case, for little endian, the it instruction > covers more since reveq isn't included and having the beq not last in > the block I think is unpredictable. If you really want to optimise the > big endian case not to have an additional it generated by gas, you can > write ittt so that beq is included with little endian but not with big > endian. I wouldn't bother much for an extra it anyway. I think the itttt is correct. Unless you wish to illustrate why you think it's wrong by pasting the code and showing why you think the beq isn't the last instruction... > > ?? ? ? ?tst ? ? r3, #PSR_T_BIT > > ?? ? ? ?subeq ? r4, r2, #4 > > 1: ? ? ?ldreqt ?r0, [r4] > > ?? ? ? ?reveq ? r0, r0 > > ?? ? ? ?beq ? ? call_fpe > > You can have the T bit set but the instruction a 32-bit Thumb in which > case r2 is in the middle of such instruction rather than the next. > Unless you only refer to the ARM mode, in which case the comment is > fine. So? I'm confused why you're making a mountain out of apparantly nothing.