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From: Hans Rosenfeld <hans.rosenfeld@amd.com>
To: Ingo Molnar <mingo@elte.hu>
Cc: "hpa@zytor.com" <hpa@zytor.com>,
	"tglx@linutronix.de" <tglx@linutronix.de>,
	"Herrmann3, Andreas" <Andreas.Herrmann3@amd.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"x86@kernel.org" <x86@kernel.org>
Subject: Re: [PATCH 4/4] x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs
Date: Thu, 27 Jan 2011 12:50:17 +0100	[thread overview]
Message-ID: <20110127115017.GH877@escobedo.osrc.amd.com> (raw)
In-Reply-To: <20110126205608.GA14361@elte.hu>

On Wed, Jan 26, 2011 at 03:56:08PM -0500, Ingo Molnar wrote:
> * Hans Rosenfeld <hans.rosenfeld@amd.com> wrote:
> > +#ifdef CONFIG_SMP
> > +int amd_get_subcaches(int cpu)
> 
> Well, sprinkling it with CONFIG_SMP is pretty ugly. Also, there's no fundamental 
> reason why this shouldnt work with UP. Yes, it makes most sense on SMP but such code 
> should be SMP-invariant.

True, it is pretty ugly. And while the feature is pretty useless for UP,
it would still work for compute_unit_id 0 in that case.

The problem is that cpuinfo_x86.compute_unit_id etc. don't exist unless
CONFIG_SMP is enabled. I don't think there is any reason why this should
be that way, but changing this just for this particular L3 feature seems
too intrusive. Do you really want me to do that?


Hans


-- 
%SYSTEM-F-ANARCHISM, The operating system has been overthrown


  reply	other threads:[~2011-01-27 12:05 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-01-24 15:05 [PATCH 0/4] x86, amd: family 0x15 L3 cache features Hans Rosenfeld
2011-01-24 15:05 ` [PATCH 1/4] x86, amd: Normalize compute unit IDs on multi-node processors Hans Rosenfeld
2011-01-26 10:57   ` [tip:x86/amd-nb] " tip-bot for Andreas Herrmann
2011-02-14 14:30     ` Ingo Molnar
2011-02-14 17:14       ` [PATCH] x86, amd: Fix uninitialized variable warning Borislav Petkov
2011-02-15  3:10         ` [tip:x86/amd-nb] x86, amd: Initialize variable properly tip-bot for Borislav Petkov
2011-02-04 22:07   ` [PATCH 1/4] x86, amd: Normalize compute unit IDs on multi-node processors Andrew Morton
2011-01-24 15:05 ` [PATCH 2/4] x86, amd: Enable L3 cache index disable on family 0x15 Hans Rosenfeld
2011-01-26 10:58   ` [tip:x86/amd-nb] " tip-bot for Hans Rosenfeld
2011-01-24 15:05 ` [PATCH 3/4] x86, amd: Extend AMD northbridge caching code to support "Link Control" devices Hans Rosenfeld
2011-01-26 10:58   ` [tip:x86/amd-nb] " tip-bot for Hans Rosenfeld
2011-01-24 15:05 ` [PATCH 4/4] x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs Hans Rosenfeld
2011-01-26 10:56   ` Ingo Molnar
2011-01-26 17:05     ` Hans Rosenfeld
2011-01-26 17:08     ` Hans Rosenfeld
2011-01-26 20:56       ` Ingo Molnar
2011-01-27 11:50         ` Hans Rosenfeld [this message]
2011-01-27 12:47           ` Ingo Molnar
2011-02-01 15:14             ` Hans Rosenfeld
2011-02-07 17:10             ` Hans Rosenfeld
2011-02-08 12:03               ` [tip:x86/amd-nb] " tip-bot for Hans Rosenfeld
  -- strict thread matches above, loose matches on Subject: below --
2010-12-20 17:13 [PATCH 0/4] x86, amd: family 0x15 L3 cache features Hans Rosenfeld
2010-12-20 17:13 ` [PATCH 4/4] x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs Hans Rosenfeld

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