Re: [Qemu-devel] [PATCH 7/7] ahci: work around bug with level interrupts

From: Aurelien Jarno <aurelien@aurel32.net>
To: Alexander Graf <agraf@suse.de>
Cc: Kevin Wolf <kwolf@redhat.com>,
	Joerg Roedel <Joerg.Roedel@amd.com>,
	qemu-devel Developers <qemu-devel@nongnu.org>,
	Sebastian Herbszt <herbszt@gmx.de>
Subject: Re: [Qemu-devel] [PATCH 7/7] ahci: work around bug with level interrupts
Date: Tue, 1 Feb 2011 17:34:53 +0100	[thread overview]
Message-ID: <20110201163453.GB7112@hall.aurel32.net> (raw)
In-Reply-To: <1296571892-12702-8-git-send-email-agraf@suse.de>

On Tue, Feb 01, 2011 at 03:51:32PM +0100, Alexander Graf wrote:
> When using level based interrupts, the interrupt is treated the same as an
> edge triggered one: leaving the line up does not retrigger the interrupt.
> 
> In fact, when not lowering the line, we won't ever get a new interrupt inside
> the guest. So let's always retrigger an interrupt as soon as the OS ack'ed
> something on the device. This way we're sure the guest doesn't starve on
> interrupts until someone fixes the actual interrupt path.

Given this issue mostly concerns x86 and not other architectures where
the SATA emulation can probably be used, what about putting the two
versions of the codes like in i8259.c:

| * all targets should do this rather than acking the IRQ in the cpu */
| #if defined(TARGET_MIPS) || defined(TARGET_PPC) || defined(TARGET_ALPHA)

The list of architectures here is reduced given the few architectures 
that actually use the i8259, so for ahci.c it should probably be #if not
defined(TARGET_I386) instead.

-- 
Aurelien Jarno	                        GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net