From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=59196 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PkJlX-0008Vu-2t for qemu-devel@nongnu.org; Tue, 01 Feb 2011 12:11:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PkJgH-000366-Az for qemu-devel@nongnu.org; Tue, 01 Feb 2011 12:06:18 -0500 Received: from hall.aurel32.net ([88.191.126.93]:36479) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PkJgH-00035s-2e for qemu-devel@nongnu.org; Tue, 01 Feb 2011 12:06:17 -0500 Date: Tue, 1 Feb 2011 18:06:14 +0100 From: Aurelien Jarno Subject: Re: [Qemu-devel] [PATCH 7/7] ahci: work around bug with level interrupts Message-ID: <20110201170614.GC7112@hall.aurel32.net> References: <1296571892-12702-1-git-send-email-agraf@suse.de> <1296571892-12702-8-git-send-email-agraf@suse.de> <20110201163453.GB7112@hall.aurel32.net> <8C700D49-A77C-4FC6-850D-AFBD7DBBBF1C@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <8C700D49-A77C-4FC6-850D-AFBD7DBBBF1C@suse.de> Sender: Aurelien Jarno List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: Kevin Wolf , Joerg Roedel , qemu-devel Developers , Sebastian Herbszt On Tue, Feb 01, 2011 at 05:53:43PM +0100, Alexander Graf wrote: > > On 01.02.2011, at 17:34, Aurelien Jarno wrote: > > > On Tue, Feb 01, 2011 at 03:51:32PM +0100, Alexander Graf wrote: > >> When using level based interrupts, the interrupt is treated the same as an > >> edge triggered one: leaving the line up does not retrigger the interrupt. > >> > >> In fact, when not lowering the line, we won't ever get a new interrupt inside > >> the guest. So let's always retrigger an interrupt as soon as the OS ack'ed > >> something on the device. This way we're sure the guest doesn't starve on > >> interrupts until someone fixes the actual interrupt path. > > > > Given this issue mostly concerns x86 and not other architectures where > > the SATA emulation can probably be used, what about putting the two > > versions of the codes like in i8259.c: > > > > | * all targets should do this rather than acking the IRQ in the cpu */ > > | #if defined(TARGET_MIPS) || defined(TARGET_PPC) || defined(TARGET_ALPHA) > > > > The list of architectures here is reduced given the few architectures > > that actually use the i8259, so for ahci.c it should probably be #if not > > defined(TARGET_I386) instead. > > Because then we'd have to build the ahci code conditionally on the architecture. Right now it builds into libhw :) If we want to keep it in libhw, it's probably better to disable it on other architectures than i386. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net