From mboxrd@z Thu Jan 1 00:00:00 1970 From: Russell King - ARM Linux Subject: Re: [PATCH v2 04/28] ARM: mm: cache-l2x0: Add support for re-enabling l2x0 Date: Sat, 5 Feb 2011 09:47:30 +0000 Message-ID: <20110205094730.GA23965@n2100.arm.linux.org.uk> References: <1295834493-5019-5-git-send-email-ccross@android.com> <1295968464.10109.264.camel@e102109-lin.cambridge.arm.com> <20110125154133.GB17280@n2100.arm.linux.org.uk> <1295979242.10109.308.camel@e102109-lin.cambridge.arm.com> <2f97ec8a084e590220e1548fc927b60e@mail.gmail.com> <-8932138696981683633@unknownmsgid> <20110204234331.GF8732@n2100.arm.linux.org.uk> <1bebe4b5c8590059b70a146d5486fa6a@mail.gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <1bebe4b5c8590059b70a146d5486fa6a-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Santosh Shilimkar Cc: Colin Cross , Will Deacon , Catalin Marinas , Linus Walleij , konkers-z5hGa2qSFaRBDgjK7y7TUQ@public.gmane.org, Tony Lindgren , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: linux-tegra@vger.kernel.org On Sat, Feb 05, 2011 at 01:21:24PM +0530, Santosh Shilimkar wrote: > GIC save/restore on OMAP follows different strategy. There is a > Predefined layout to save content and restore is done atomically > by boot ROM code. > L2 cache also same case. Only AUXCTRL needs to be programmed on > wakeup from low power mode and that too with secure call. Rest > of the registers are managed by boot ROM code. > > TWD is already managed through framework. Othe CPU low power > sequence is very small and OMAP has restrictions on the last > core to go down and first to wakeup. > > So at least I don't see any use of common notifiers for GIC > and L2 will help OMAP lower power code. What this means is that we're going to end up littering things like GIC and other stuff with lots of individual SoC specific code to save state into individual SoC specific structures. This is not sane, and we're not going to corrupt generic code with SoC specific code. -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751753Ab1BEJsZ (ORCPT ); Sat, 5 Feb 2011 04:48:25 -0500 Received: from caramon.arm.linux.org.uk ([78.32.30.218]:51178 "EHLO caramon.arm.linux.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750787Ab1BEJsX (ORCPT ); Sat, 5 Feb 2011 04:48:23 -0500 Date: Sat, 5 Feb 2011 09:47:30 +0000 From: Russell King - ARM Linux To: Santosh Shilimkar Cc: Colin Cross , Will Deacon , Catalin Marinas , Linus Walleij , konkers@android.com, Tony Lindgren , linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, olof@lixom.net, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 04/28] ARM: mm: cache-l2x0: Add support for re-enabling l2x0 Message-ID: <20110205094730.GA23965@n2100.arm.linux.org.uk> References: <1295834493-5019-5-git-send-email-ccross@android.com> <1295968464.10109.264.camel@e102109-lin.cambridge.arm.com> <20110125154133.GB17280@n2100.arm.linux.org.uk> <1295979242.10109.308.camel@e102109-lin.cambridge.arm.com> <2f97ec8a084e590220e1548fc927b60e@mail.gmail.com> <-8932138696981683633@unknownmsgid> <20110204234331.GF8732@n2100.arm.linux.org.uk> <1bebe4b5c8590059b70a146d5486fa6a@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1bebe4b5c8590059b70a146d5486fa6a@mail.gmail.com> User-Agent: Mutt/1.5.19 (2009-01-05) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Feb 05, 2011 at 01:21:24PM +0530, Santosh Shilimkar wrote: > GIC save/restore on OMAP follows different strategy. There is a > Predefined layout to save content and restore is done atomically > by boot ROM code. > L2 cache also same case. Only AUXCTRL needs to be programmed on > wakeup from low power mode and that too with secure call. Rest > of the registers are managed by boot ROM code. > > TWD is already managed through framework. Othe CPU low power > sequence is very small and OMAP has restrictions on the last > core to go down and first to wakeup. > > So at least I don't see any use of common notifiers for GIC > and L2 will help OMAP lower power code. What this means is that we're going to end up littering things like GIC and other stuff with lots of individual SoC specific code to save state into individual SoC specific structures. This is not sane, and we're not going to corrupt generic code with SoC specific code. From mboxrd@z Thu Jan 1 00:00:00 1970 From: linux@arm.linux.org.uk (Russell King - ARM Linux) Date: Sat, 5 Feb 2011 09:47:30 +0000 Subject: [PATCH v2 04/28] ARM: mm: cache-l2x0: Add support for re-enabling l2x0 In-Reply-To: <1bebe4b5c8590059b70a146d5486fa6a@mail.gmail.com> References: <1295834493-5019-5-git-send-email-ccross@android.com> <1295968464.10109.264.camel@e102109-lin.cambridge.arm.com> <20110125154133.GB17280@n2100.arm.linux.org.uk> <1295979242.10109.308.camel@e102109-lin.cambridge.arm.com> <2f97ec8a084e590220e1548fc927b60e@mail.gmail.com> <-8932138696981683633@unknownmsgid> <20110204234331.GF8732@n2100.arm.linux.org.uk> <1bebe4b5c8590059b70a146d5486fa6a@mail.gmail.com> Message-ID: <20110205094730.GA23965@n2100.arm.linux.org.uk> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Sat, Feb 05, 2011 at 01:21:24PM +0530, Santosh Shilimkar wrote: > GIC save/restore on OMAP follows different strategy. There is a > Predefined layout to save content and restore is done atomically > by boot ROM code. > L2 cache also same case. Only AUXCTRL needs to be programmed on > wakeup from low power mode and that too with secure call. Rest > of the registers are managed by boot ROM code. > > TWD is already managed through framework. Othe CPU low power > sequence is very small and OMAP has restrictions on the last > core to go down and first to wakeup. > > So at least I don't see any use of common notifiers for GIC > and L2 will help OMAP lower power code. What this means is that we're going to end up littering things like GIC and other stuff with lots of individual SoC specific code to save state into individual SoC specific structures. This is not sane, and we're not going to corrupt generic code with SoC specific code.