[U-Boot] [PATCHv2] fsl_ddr: Don't use full 64-bit divides on 32-bit PowerPC

From: Wolfgang Denk <wd@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCHv2] fsl_ddr: Don't use full 64-bit divides on 32-bit PowerPC
Date: Wed, 13 Apr 2011 22:50:13 +0200	[thread overview]
Message-ID: <20110413205013.E4FD014F02E@gemini.denx.de> (raw)
In-Reply-To: <1298478920-22044-1-git-send-email-Kyle.D.Moffett@boeing.com>

Dear Kyle Moffett,

In message <1298478920-22044-1-git-send-email-Kyle.D.Moffett@boeing.com> you wrote:
> The current FreeScale MPC-8xxx DDR SPD interpreter is using full 64-bit
> integer divide operations to convert between nanoseconds and DDR clock
> cycles given arbitrary DDR clock frequencies.
...
> +/* To avoid 64-bit full-divides, we factor this here */
> +#define ULL_2e12 2000000000000ULL
> +#define UL_5pow12 244140625UL
> +#define UL_2pow13 (1UL << 13)
> +
> +#define ULL_8Fs 0xFFFFFFFFULL

We don't allow CamelCaps macro names. Macros are all caps, please.

Best regards,

Wolfgang Denk

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