From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 12/13] drm/i915: Prevent mixing of snooped and tiling modes for old chipsets Date: Thu, 14 Apr 2011 19:43:35 +0200 Message-ID: <20110414174334.GG3408@viiv.ffwll.ch> References: <1302771827-26112-1-git-send-email-chris@chris-wilson.co.uk> <1302771827-26112-13-git-send-email-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-wy0-f177.google.com (mail-wy0-f177.google.com [74.125.82.177]) by gabe.freedesktop.org (Postfix) with ESMTP id BC4579E76C for ; Thu, 14 Apr 2011 10:43:41 -0700 (PDT) Received: by wyb28 with SMTP id 28so2052432wyb.36 for ; Thu, 14 Apr 2011 10:43:41 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1302771827-26112-13-git-send-email-chris@chris-wilson.co.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Chris Wilson Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Apr 14, 2011 at 10:03:46AM +0100, Chris Wilson wrote: > Older chipsets do not support snooping (i.e. cache sharing between the > CPU and GPU) on tiled surfaces. So prevent userspace from being silly > should we one day expose the ability to change cache levels from > userspace. > > It does enforce a strict ordering for mode changing though. So in order > to change a buffer to snooped, the driver has to clear any tiling first > and then change the cache level. This is consistent with how we flush > and update the PTEs and seems a reasonable imposition on the driver. > Deferring the check until use, whilst providing flexibilty here, implies > forcing extra unbinds and a more complicated error message from, for > example, execbuffer. Reviewed-by: Daniel Vetter Small error in the debug output below. > diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c > index 281ad3d..ca69fd4 100644 > --- a/drivers/gpu/drm/i915/i915_gem_tiling.c > +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c > @@ -331,6 +331,14 @@ i915_gem_set_tiling(struct drm_device *dev, void *data, > } > > mutex_lock(&dev->struct_mutex); > + if (INTEL_INFO(dev)->gen < 6 && > + args->tiling_mode != I915_TILING_NONE && > + obj->cache_level != I915_CACHE_NONE) { > + DRM_DEBUG("can't not set a tiling mode on snooped memory," One negation too much. > + "it must be linear for pre-SandyBridge chipsets\n"); > + ret = -EINVAL; > + goto err; > + } > if (args->tiling_mode != obj->tiling_mode || > args->stride != obj->stride) { > /* We need to rebind the object if its current allocation -- Daniel Vetter Mail: daniel@ffwll.ch Mobile: +41 (0)79 365 57 48