From mboxrd@z Thu Jan  1 00:00:00 1970
From: Wei Wang2 <wei.wang2@amd.com>
Subject: Re: [RFC PATCH 0/3] AMD IOMMU: Share p2m table with iommu
Date: Mon, 23 May 2011 14:08:49 +0200
Message-ID: <201105231408.50575.wei.wang2@amd.com>
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To: Tim Deegan <Tim.Deegan@citrix.com>
Cc: "Zhang, Yang Z" <yang.z.zhang@intel.com>, "xen-devel@lists.xensource.com" <xen-devel@lists.xensource.com>, "Kay, Allen M" <allen.m.kay@intel.com>
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On Monday 23 May 2011 12:58:00 Tim Deegan wrote:
> Hi,
>
> At 01:51 +0100 on 21 May (1305942710), Kay, Allen M wrote:
> > The common code that caused problem is the following.
> >
> > typedef enum {
> > -    p2m_invalid = 0,            /* Nothing mapped here */
> > -    p2m_ram_rw = 1,             /* Normal read/write guest RAM */
> > +    p2m_ram_rw = 0,             /* Normal read/write guest RAM */
> > +    p2m_invalid = 1,            /* Nothing mapped here */
> >
> > With the above change, guest with device direct assignment fails to
> > boot.  QEMU VGA displays some weird color patterns.
>
> Unfortunately this change seems to be necessary for AMD IOMMU to share
> pagetables with the p2m.  I'd rather we didn't have it, because it means
> empty ptes look like RAM mappings of frame 0. :(
>
> Wei, is there any way we can reorganise the AMD IOMMU pagetables so we
> can store the p2m type somewhere that's not required to be zero?  If
> not, I'm inclined to revert the p2m-sharing for AMD IOMMUs, since at the
> very least we'd like to be able to handle types other than ram_rw
> (e.g. ram_ro).
Tim,
Theoretically, we just need to keep bit 52 - bit 58 all zero for valid dma 
translation entry. Probably we could  define ram_rw as 11000000000b, 
which is the valid r/w permission for iommu and leaves bit 52 - 58 zero? 
Thanks,
Wei

> In the meantime, Allen, does the attached patch make things any better
> for you?
>
> Cheers,
>
> Tim.