From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:42642) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QzB9g-0000OT-Eg for qemu-devel@nongnu.org; Thu, 01 Sep 2011 13:34:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QzB9f-0008WR-AO for qemu-devel@nongnu.org; Thu, 01 Sep 2011 13:34:20 -0400 Received: from mx1.redhat.com ([209.132.183.28]:20805) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QzB9f-0008WN-2C for qemu-devel@nongnu.org; Thu, 01 Sep 2011 13:34:19 -0400 Date: Thu, 1 Sep 2011 19:34:01 +0300 From: "Michael S. Tsirkin" Message-ID: <20110901163359.GB11620@redhat.com> References: <1314857389-13363-1-git-send-email-david@gibson.dropbear.id.au> <20110901153020.GB10989@redhat.com> <4E5FAF6A.70205@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4E5FAF6A.70205@redhat.com> Subject: Re: [Qemu-devel] [PATCH] virtio: Make memory barriers be memory barriers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini Cc: aliguori@us.ibm.com, aik@ozlabs.ru, rusty@rustcorp.com.au, agraf@suse.de, qemu-devel@nongnu.org, David Gibson On Thu, Sep 01, 2011 at 06:14:34PM +0200, Paolo Bonzini wrote: > On 09/01/2011 05:30 PM, Michael S. Tsirkin wrote: > >>> The virtio code already has memory barrier wmb() macros in the code. > >>> However they are was defined as no-ops. The comment claims that real > >>> barriers are not necessary because the code does not run concurrent. > >>> However, with kvm and io-thread enabled, this is not true and this qemu > >>> code can indeed run concurrently with the guest kernel. This does not > >>> cause problems on x86 due to it's strongly ordered storage model, but it > >>> causes a race leading to virtio errors on POWER which has a relaxed storage > >>> ordering model. > > > >Why not limit the change to ppc then? > > Because the bug is masked by the x86 memory model, but it is still > there even there conceptually. It is not really true that x86 does > not need memory barriers, though it doesn't in this case: > > http://bartoszmilewski.wordpress.com/2008/11/05/who-ordered-memory-fences-on-an-x86/ > > Paolo Right. To summarize, on x86 we probably want wmb and rmb to be compiler barrier only. Only mb might in theory need to be an mfence. But there might be reasons why that is not an issue either if we look closely enough. -- MST