From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:50584) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R54tV-0005Tt-Ne for qemu-devel@nongnu.org; Sat, 17 Sep 2011 20:06:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1R54tU-0001nV-Ks for qemu-devel@nongnu.org; Sat, 17 Sep 2011 20:06:01 -0400 Received: from dns1.mips.com ([12.201.5.69]:57510) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R54tU-0001mm-Dp for qemu-devel@nongnu.org; Sat, 17 Sep 2011 20:06:00 -0400 Date: Sat, 17 Sep 2011 17:05:32 -0700 From: Eric Johnson Message-ID: <20110918000532.GA28991@linux-ericj.mips.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline Subject: [Qemu-devel] [PATCH] Add privilege level check to several Cop0 instructions. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, aurelien@aurel32.net The MIPS Architecture Verification Programs (AVPs) check privileged instructions for the required privilege level. These changes are needed to pass the AVP suite. Signed-off-by: Eric Johnson --- target-mips/translate.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index d5b1c76..d99a716 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -5940,6 +5940,8 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int { const char *opn = "ldst"; + check_cp0_enabled(ctx); + switch (opc) { case OPC_MFC0: if (rt == 0) { @@ -10125,6 +10127,7 @@ static void gen_pool32axf (CPUState *env, DisasContext *ctx, int rt, int rs, #ifndef CONFIG_USER_ONLY case MFC0: case MFC0 + 32: + check_cp0_enabled(ctx); if (rt == 0) { /* Treat as NOP. */ break; @@ -10136,6 +10139,7 @@ static void gen_pool32axf (CPUState *env, DisasContext *ctx, int rt, int rs, { TCGv t0 = tcg_temp_new(); + check_cp0_enabled(ctx); gen_load_gpr(t0, rt); gen_mtc0(env, ctx, t0, rs, (ctx->opcode >> 11) & 0x7); tcg_temp_free(t0); @@ -10230,10 +10234,12 @@ static void gen_pool32axf (CPUState *env, DisasContext *ctx, int rt, int rs, switch (minor) { case RDPGPR: check_insn(env, ctx, ISA_MIPS32R2); + check_cp0_enabled(ctx); gen_load_srsgpr(rt, rs); break; case WRPGPR: check_insn(env, ctx, ISA_MIPS32R2); + check_cp0_enabled(ctx); gen_store_srsgpr(rt, rs); break; default: @@ -10276,6 +10282,7 @@ static void gen_pool32axf (CPUState *env, DisasContext *ctx, int rt, int rs, { TCGv t0 = tcg_temp_new(); + check_cp0_enabled(ctx); save_cpu_state(ctx, 1); gen_helper_di(t0); gen_store_gpr(t0, rs); @@ -10288,6 +10295,7 @@ static void gen_pool32axf (CPUState *env, DisasContext *ctx, int rt, int rs, { TCGv t0 = tcg_temp_new(); + check_cp0_enabled(ctx); save_cpu_state(ctx, 1); gen_helper_ei(t0); gen_store_gpr(t0, rs); @@ -10765,6 +10773,7 @@ static void decode_micromips32_opc (CPUState *env, DisasContext *ctx, minor = (ctx->opcode >> 12) & 0xf; switch (minor) { case CACHE: + check_cp0_enabled(ctx); /* Treat as no-op. */ break; case LWC2: @@ -12216,6 +12225,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx, int *is_branch) break; case OPC_CACHE: check_insn(env, ctx, ISA_MIPS3 | ISA_MIPS32); + check_cp0_enabled(ctx); /* Treat as NOP. */ break; case OPC_PREF: