From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:50287) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R55FR-0008Ra-Gw for qemu-devel@nongnu.org; Sat, 17 Sep 2011 20:28:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1R55FQ-0007F0-Cr for qemu-devel@nongnu.org; Sat, 17 Sep 2011 20:28:41 -0400 Received: from dns1.mips.com ([12.201.5.69]:44197) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1R55FQ-0007Eu-41 for qemu-devel@nongnu.org; Sat, 17 Sep 2011 20:28:40 -0400 Date: Sat, 17 Sep 2011 17:28:16 -0700 From: Eric Johnson Message-ID: <20110918002816.GA10076@linux-ericj.mips.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline Subject: [Qemu-devel] [PATCH] Allow microMIPS SWP and SDP to have RD equal to BASE. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, aurelien@aurel32.net The microMIPS SWP and SDP instructions do not modify GPRs. So their behavior is well defined when RD equals BASE. The MIPS Architecture Verification Programs (AVPs) check that they work as expected. This is required for AVPs to pass. Signed-off-by: Eric Johnson --- target-mips/translate.c | 10 +++++++++- 1 files changed, 9 insertions(+), 1 deletions(-) The patch applies to a8467c7a0e8b024a18608ff7db31ca2f2297e641. diff --git a/target-mips/translate.c b/target-mips/translate.c index d5b1c76..82cf75b 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -10034,7 +10034,7 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, const char *opn = "ldst_pair"; TCGv t0, t1; - if (ctx->hflags & MIPS_HFLAG_BMASK || rd == 31 || rd == base) { + if (ctx->hflags & MIPS_HFLAG_BMASK || rd == 31) { generate_exception(ctx, EXCP_RI); return; } @@ -10046,6 +10046,10 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, switch (opc) { case LWP: + if (rd == base) { + generate_exception(ctx, EXCP_RI); + return; + } save_cpu_state(ctx, 0); op_ld_lw(t1, t0, ctx); gen_store_gpr(t1, rd); @@ -10067,6 +10071,10 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, break; #ifdef TARGET_MIPS64 case LDP: + if (rd == base) { + generate_exception(ctx, EXCP_RI); + return; + } save_cpu_state(ctx, 0); op_ld_ld(t1, t0, ctx); gen_store_gpr(t1, rd);