linux-next: manual merge of the s5p tree with the arm tree

From: Stephen Rothwell <sfr@canb.auug.org.au>
To: Kukjin Kim <kgene.kim@samsung.com>
Cc: linux-next@vger.kernel.org, linux-kernel@vger.kernel.org,
	Marc Zyngier <marc.zyngier@arm.com>,
	Russell King <rmk@arm.linux.org.uk>,
	Thomas Abraham <thomas.abraham@linaro.org>
Subject: linux-next: manual merge of the s5p tree with the arm tree
Date: Tue, 22 Nov 2011 13:01:59 +1100	[thread overview]
Message-ID: <20111122130159.ba1426acb6e340c6f906d9b5@canb.auug.org.au> (raw)

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Hi Kukjin,

Today's linux-next merge of the s5p tree got a conflict in
arch/arm/mach-exynos/cpu.c between commit db0d4db22a78 ("ARM: gic: allow
GIC to support non-banked setups") from the  tree and commit fae3f1696b33
("ARM: EXYNOS: Enable conversion of GIC dt irq specifier to linux virq")
from the s5p tree.

I fixed it up (see below) and can carry the fix as necessary.
-- 
Cheers,
Stephen Rothwell                    sfr@canb.auug.org.au

diff --cc arch/arm/mach-exynos/cpu.c
index 6e34485,8e09f34..0000000

--- a/arch/arm/mach-exynos/cpu.c
+++ b/arch/arm/mach-exynos/cpu.c
@@@ -206,6 -231,24 +230,13 @@@ void __init exynos4_init_clocks(int xta
  	exynos4_setup_clocks();
  }
  
 -static void exynos4_gic_irq_fix_base(struct irq_data *d)
 -{
 -	struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
 -
 -	gic_data->cpu_base = S5P_VA_GIC_CPU +
 -			    (gic_bank_offset * smp_processor_id());
 -
 -	gic_data->dist_base = S5P_VA_GIC_DIST +
 -			    (gic_bank_offset * smp_processor_id());
 -}
 -
+ #ifdef CONFIG_OF
+ static const struct of_device_id exynos4_dt_irq_match[] = {
+ 	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+ 	{},
+ };
+ #endif
+ 
  void __init exynos4_init_irq(void)
  {
  	int irq;
@@@ -213,8 -255,17 +244,13 @@@
  
  	gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
  
- 	gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset);
+ 	if (!of_have_populated_dt())
 -		gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
++		gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset);
+ #ifdef CONFIG_OF
+ 	else
+ 		of_irq_init(exynos4_dt_irq_match);
+ #endif
  
 -	gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
 -	gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
 -	gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;
 -
  	for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
  
  		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),

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