From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Sun, 8 Jan 2012 11:51:30 +0100 Subject: [U-Boot] Possible Denx m28evk ethernet problem + solution In-Reply-To: <67CA36CD-3416-40DC-8602-855AAD3EEB9A@delien.nl> References: <3C18F794-D414-406A-BEA4-ABE59990B5BF@Delien.nl> <67CA36CD-3416-40DC-8602-855AAD3EEB9A@delien.nl> Message-ID: <201201081151.30796.marek.vasut@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de > > Please use Stefano's imx git tree, which has support for mx28evk already. > > Thanks for the heads-up. It's a bit confusing and unexpected to have a > mainline spread across different git trees; Will Stefano's mainline be > integrated into the main-mainline sometime? Not really ... that's how it all works. When Stefano sends pull RQ, it'll go mainline. > > > m28evk and mx28evk differ in the way they driver their Ethernet PHYs. > > Yes, Marek has patiently explained that to me; It's all clear now. But it > was a good exercise because our product board has a different phy too. > > > Let me know if you have any issues. > > I have a question: The auto-detected SDRAM size is parsed form SPL to > U-Boot through both scrathch1 and scratch2, probably as a safeguard not to > assume any value to be a valid one. Did you ever see the error or > different scratch values occur? I never did. But what I do see occur every > now and then is a value of 0 in both registers, mostly after obscure reset > scenarios. I see no problems with the board DRAM detection on our board, no. I tested this quite thoroughly. I don't see the registers differ either ... ever. I suspect your problem is with your DRAM configuration data -- if your DRAM chip is misconfigured, you'll get such memory problems. > > Can we agree on a different algo to determine the validity of SDRAM size? > I'm thinking somewhere around the line of a power of 2 between 2MiB and > 1GiB. Preferable I'd like to use only 1 scratch register for that. The > other scratch register could then be used to store the boot-mode value > during SPL stage. The boot mode value is useful for boards capable of > booting from different MMC devices, like ours. RFC/patch is always welcome. > > BTW: My version has both MMCs, both Ethernet intefaces and NAND working for > the evk. MX28EVK has no NAND if I understand it correctly. > I have also typed in regs-digctl.h. I can send you or Stefano my > files, if they're any use to you. Make a patch and submit to the mailing list, like everyone else does please. Don't try to reinvent wheel ... square one this time even. > > Cheers, > > Robert. M