From mboxrd@z Thu Jan 1 00:00:00 1970 From: Will Deacon Subject: Re: oprofile and ARM A9 hardware counter Date: Fri, 27 Jan 2012 13:56:46 +0000 Message-ID: <20120127135646.GE2347@mudshark.cambridge.arm.com> References: <20120127121311.GB2347@mudshark.cambridge.arm.com> <20120127132826.GD2347@mudshark.cambridge.arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: oprofile-list-bounces@lists.sourceforge.net To: =?iso-8859-1?Q?M=E5ns_Rullg=E5rd?= Cc: "Cousson, Benoit" , Ming Lei , "oprofile-list@lists.sourceforge.net" , "eranian@gmail.com" , "linux-omap@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" List-Id: linux-omap@vger.kernel.org On Fri, Jan 27, 2012 at 01:47:01PM +0000, M=E5ns Rullg=E5rd wrote: > Will Deacon writes: > = > > Mans, > > > > On Fri, Jan 27, 2012 at 12:56:35PM +0000, M=E5ns Rullg=E5rd wrote: > >> Will Deacon writes: > >> > Did this lead anywhere in the end? It seems as though Ming Lei has a= working > >> > setup but Stephane is unable to replicate it, despite applying the n= ecessary > >> > patches and trying an updated bootloader. > >> = > >> With the patches listed above plus the one in [1], I get PMU interrupt= s. > >> However, unless I restrict the profiled process to one CPU > >> (taskset 1 perf record ...), I get a panic in armpmu_event_update() wi= th > >> the 'event' argument being null when called from armv7pmu_handle_irq(). > >> = > >> [1] http://article.gmane.org/gmane.linux.ports.arm.omap/69696 > > > > Great, thanks for trying this out. Which version of the kernel were you > > using? I fixed a bunch of NULL pointer derefs. during the 3.2 window, b= ut if > > you were using an -rc kernel you have have hit one of them. > = > This was with the Linaro tilt-3.2 kernel from > git://git.linaro.org/landing-teams/working/ti/kernel.git, commit > 73e2c294444f209d281f7cd10b52b53b087e74f1. Maybe one of the many patches > it has on top of 3.2 is to blame. Perhaps, or (more likely) the interrupt affinity for the CTI isn't working properly and the interrupt is always delivered to CPU0. I'll keep this in mind in case we get any more reports like this. Cheers, Will ---------------------------------------------------------------------------= --- Try before you buy =3D See our experts in action! The most comprehensive online learning library for Microsoft developers is just $99.99! Visual Studio, SharePoint, SQL - plus HTML5, CSS3, MVC3, Metro Style Apps, more. Free future releases when you subscribe now! http://p.sf.net/sfu/learndevnow-dev2 From mboxrd@z Thu Jan 1 00:00:00 1970 From: will.deacon@arm.com (Will Deacon) Date: Fri, 27 Jan 2012 13:56:46 +0000 Subject: oprofile and ARM A9 hardware counter In-Reply-To: References: <20120127121311.GB2347@mudshark.cambridge.arm.com> <20120127132826.GD2347@mudshark.cambridge.arm.com> Message-ID: <20120127135646.GE2347@mudshark.cambridge.arm.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, Jan 27, 2012 at 01:47:01PM +0000, M?ns Rullg?rd wrote: > Will Deacon writes: > > > Mans, > > > > On Fri, Jan 27, 2012 at 12:56:35PM +0000, M?ns Rullg?rd wrote: > >> Will Deacon writes: > >> > Did this lead anywhere in the end? It seems as though Ming Lei has a working > >> > setup but Stephane is unable to replicate it, despite applying the necessary > >> > patches and trying an updated bootloader. > >> > >> With the patches listed above plus the one in [1], I get PMU interrupts. > >> However, unless I restrict the profiled process to one CPU > >> (taskset 1 perf record ...), I get a panic in armpmu_event_update() with > >> the 'event' argument being null when called from armv7pmu_handle_irq(). > >> > >> [1] http://article.gmane.org/gmane.linux.ports.arm.omap/69696 > > > > Great, thanks for trying this out. Which version of the kernel were you > > using? I fixed a bunch of NULL pointer derefs. during the 3.2 window, but if > > you were using an -rc kernel you have have hit one of them. > > This was with the Linaro tilt-3.2 kernel from > git://git.linaro.org/landing-teams/working/ti/kernel.git, commit > 73e2c294444f209d281f7cd10b52b53b087e74f1. Maybe one of the many patches > it has on top of 3.2 is to blame. Perhaps, or (more likely) the interrupt affinity for the CTI isn't working properly and the interrupt is always delivered to CPU0. I'll keep this in mind in case we get any more reports like this. Cheers, Will