From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:46705) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S8JTw-0001Pl-Nh for qemu-devel@nongnu.org; Thu, 15 Mar 2012 18:49:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S8JTt-0004bW-QP for qemu-devel@nongnu.org; Thu, 15 Mar 2012 18:49:16 -0400 Received: from mail.serverraum.org ([78.47.150.89]:40877) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S8JTt-0004bR-D2 for qemu-devel@nongnu.org; Thu, 15 Mar 2012 18:49:13 -0400 From: Michael Walle Date: Thu, 15 Mar 2012 23:42:12 +0100 References: <1330893156-26569-1-git-send-email-afaerber@suse.de> <1331747617-7837-1-git-send-email-afaerber@suse.de> <1331747617-7837-10-git-send-email-afaerber@suse.de> In-Reply-To: <1331747617-7837-10-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: Text/Plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <201203152342.12399.michael@walle.cc> Subject: Re: [Qemu-devel] [RFC 09/12] target-lm32: QOM'ify CPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Andreas =?utf-8?q?F=C3=A4rber?= Cc: qemu-devel@nongnu.org Am Mittwoch 14 M=C3=A4rz 2012, 18:53:33 schrieb Andreas F=C3=A4rber: > Let cpu_lm32_list() enumerate CPU classes sorted alphabetically. >=20 > Signed-off-by: Andreas F=C3=A4rber > --- > Makefile.target | 1 + > target-lm32/cpu-qom.h | 77 ++++++++++++++++++++ > target-lm32/cpu.c | 188 > +++++++++++++++++++++++++++++++++++++++++++++++++ target-lm32/cpu.h |= =20 > 1 + > target-lm32/helper.c | 142 ++++++++----------------------------- > 5 files changed, 297 insertions(+), 112 deletions(-) > create mode 100644 target-lm32/cpu-qom.h > create mode 100644 target-lm32/cpu.c >=20 > diff --git a/Makefile.target b/Makefile.target > index 3b7a4da..8c8f4a8 100644 > --- a/Makefile.target > +++ b/Makefile.target > @@ -90,6 +90,7 @@ libobj-$(TARGET_ARM) +=3D neon_helper.o iwmmxt_helper.o > libobj-$(TARGET_ALPHA) +=3D cpu.o > libobj-$(TARGET_ARM) +=3D cpu.o > libobj-$(TARGET_CRIS) +=3D cpu.o > +libobj-$(TARGET_LM32) +=3D cpu.o > libobj-$(TARGET_M68K) +=3D cpu.o > ifeq ($(TARGET_BASE_ARCH), mips) > libobj-y +=3D cpu.o > diff --git a/target-lm32/cpu-qom.h b/target-lm32/cpu-qom.h > new file mode 100644 > index 0000000..dc3d434 > --- /dev/null > +++ b/target-lm32/cpu-qom.h > @@ -0,0 +1,77 @@ > +/* > + * QEMU LatticeMico32 CPU > + * > + * Copyright (c) 2012 SUSE LINUX Products GmbH > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see > + * > + */ > +#ifndef QEMU_LM32_CPU_QOM_H > +#define QEMU_LM32_CPU_QOM_H > + > +#include "qemu/cpu.h" > +#include "cpu.h" > + > +#define TYPE_LM32_CPU "lm32-cpu" > + > +#define LM32_CPU_CLASS(klass) \ > + OBJECT_CLASS_CHECK(LM32CPUClass, (klass), TYPE_LM32_CPU) > +#define LM32_CPU(obj) \ > + OBJECT_CHECK(LM32CPU, (obj), TYPE_LM32_CPU) > +#define LM32_CPU_GET_CLASS(obj) \ > + OBJECT_GET_CLASS(LM32CPUClass, (obj), TYPE_LM32_CPU) > + > +/** > + * LM32CPUClass: > + * @parent_reset: The parent class' reset handler. > + * > + * A LatticeMico32 CPU model. > + */ > +typedef struct LM32CPUClass { > + /*< private >*/ > + CPUClass parent_class; > + /*< public >*/ > + > + void (*parent_reset)(CPUState *cpu); > + > + uint32_t revision; > + uint8_t num_interrupts; > + uint8_t num_breakpoints; > + uint8_t num_watchpoints; > + uint32_t features; > +} LM32CPUClass; > + > +/** > + * LM32CPU: > + * @env: Legacy CPU state. > + * > + * A LatticeMico32 CPU. > + */ > +typedef struct LM32CPU { > + /*< private >*/ > + CPUState parent_obj; > + /*< public >*/ > + > + CPULM32State env; > +} LM32CPU; > + > +static inline LM32CPU *cris_env_get_cpu(CPULM32State *env) cris? :) > +{ > + return LM32_CPU(container_of(env, LM32CPU, env)); > +} > + > +#define ENV_GET_CPU(e) CPU(cris_env_get_cpu(e)) ditto Apart from that: Acked-by: Michael Walle > + > + > +#endif > diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c > new file mode 100644 > index 0000000..7f5308a > --- /dev/null > +++ b/target-lm32/cpu.c > @@ -0,0 +1,188 @@ > +/* > + * QEMU LatticeMico32 CPU > + * > + * Copyright (c) 2010 Michael Walle > + * Copyright (c) 2012 SUSE LINUX Products GmbH > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2.1 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see > + * > + */ > + > +#include "cpu-qom.h" > +#include "qemu-common.h" > + > +static void lm32_cpu_reset(CPUState *c) > +{ > +} > + > +/* CPU models */ > + > +typedef struct LM32CPUInfo { > + const char *name; > + uint32_t revision; > + uint8_t num_interrupts; > + uint8_t num_breakpoints; > + uint8_t num_watchpoints; > + uint32_t features; > +} LM32CPUInfo; > + > +static const LM32CPUInfo lm32_cpus[] =3D { > + { > + .name =3D "lm32-basic", > + .revision =3D 3, > + .num_interrupts =3D 32, > + .num_breakpoints =3D 4, > + .num_watchpoints =3D 4, > + .features =3D (LM32_FEATURE_SHIFT > + | LM32_FEATURE_SIGN_EXTEND > + | LM32_FEATURE_CYCLE_COUNT), > + }, > + { > + .name =3D "lm32-standard", > + .revision =3D 3, > + .num_interrupts =3D 32, > + .num_breakpoints =3D 4, > + .num_watchpoints =3D 4, > + .features =3D (LM32_FEATURE_MULTIPLY > + | LM32_FEATURE_DIVIDE > + | LM32_FEATURE_SHIFT > + | LM32_FEATURE_SIGN_EXTEND > + | LM32_FEATURE_I_CACHE > + | LM32_FEATURE_CYCLE_COUNT), > + }, > + { > + .name =3D "lm32-full", > + .revision =3D 3, > + .num_interrupts =3D 32, > + .num_breakpoints =3D 4, > + .num_watchpoints =3D 4, > + .features =3D (LM32_FEATURE_MULTIPLY > + | LM32_FEATURE_DIVIDE > + | LM32_FEATURE_SHIFT > + | LM32_FEATURE_SIGN_EXTEND > + | LM32_FEATURE_I_CACHE > + | LM32_FEATURE_D_CACHE > + | LM32_FEATURE_CYCLE_COUNT), > + } > +}; > + > +static uint32_t cfg_by_class(LM32CPUClass *def) > +{ > + uint32_t cfg =3D 0; > + > + if (def->features & LM32_FEATURE_MULTIPLY) { > + cfg |=3D CFG_M; > + } > + > + if (def->features & LM32_FEATURE_DIVIDE) { > + cfg |=3D CFG_D; > + } > + > + if (def->features & LM32_FEATURE_SHIFT) { > + cfg |=3D CFG_S; > + } > + > + if (def->features & LM32_FEATURE_SIGN_EXTEND) { > + cfg |=3D CFG_X; > + } > + > + if (def->features & LM32_FEATURE_I_CACHE) { > + cfg |=3D CFG_IC; > + } > + > + if (def->features & LM32_FEATURE_D_CACHE) { > + cfg |=3D CFG_DC; > + } > + > + if (def->features & LM32_FEATURE_CYCLE_COUNT) { > + cfg |=3D CFG_CC; > + } > + > + cfg |=3D (def->num_interrupts << CFG_INT_SHIFT); > + cfg |=3D (def->num_breakpoints << CFG_BP_SHIFT); > + cfg |=3D (def->num_watchpoints << CFG_WP_SHIFT); > + cfg |=3D (def->revision << CFG_REV_SHIFT); > + > + return cfg; > +} > + > +static void lm32_cpu_initfn(Object *obj) > +{ > + LM32CPU *cpu =3D LM32_CPU(obj); > + LM32CPUClass *klass =3D LM32_CPU_GET_CLASS(cpu); > + CPULM32State *env =3D &cpu->env; > + > + memset(env, 0, sizeof(*env)); > + cpu_exec_init(env); > + env->cpu_model_str =3D object_get_typename(obj); > + > + env->features =3D klass->features; > + env->num_bps =3D klass->num_breakpoints; > + env->num_wps =3D klass->num_watchpoints; > + env->cfg =3D cfg_by_class(klass); > + env->flags =3D 0; > + > + cpu_reset(CPU(cpu)); > +} > + > +static void lm32_cpu_class_init(ObjectClass *klass, void *data) > +{ > + CPUClass *cpu_class =3D CPU_CLASS(klass); > + LM32CPUClass *k =3D LM32_CPU_CLASS(klass); > + const LM32CPUInfo *info =3D data; > + > + k->parent_reset =3D cpu_class->reset; > + cpu_class->reset =3D lm32_cpu_reset; > + > + k->revision =3D info->revision; > + k->num_interrupts =3D info->num_interrupts; > + k->num_breakpoints =3D info->num_breakpoints; > + k->num_watchpoints =3D info->num_watchpoints; > + k->features =3D info->features; > +} > + > +static void cpu_register(const LM32CPUInfo *info) > +{ > + TypeInfo type =3D { > + .name =3D info->name, > + .parent =3D TYPE_LM32_CPU, > + .instance_size =3D sizeof(LM32CPU), > + .instance_init =3D lm32_cpu_initfn, > + .class_size =3D sizeof(LM32CPUClass), > + .class_init =3D lm32_cpu_class_init, > + .class_data =3D (void *)info, > + }; > + > + type_register_static(&type); > +} > + > +static const TypeInfo lm32_cpu_type_info =3D { > + .name =3D TYPE_LM32_CPU, > + .parent =3D TYPE_CPU, > + .instance_size =3D sizeof(LM32CPU), > + .abstract =3D true, > + .class_size =3D sizeof(LM32CPUClass), > +}; > + > +static void lm32_cpu_register_types(void) > +{ > + int i; > + > + type_register_static(&lm32_cpu_type_info); > + for (i =3D 0; i < ARRAY_SIZE(lm32_cpus); i++) { > + cpu_register(&lm32_cpus[i]); > + } > +} > + > +type_init(lm32_cpu_register_types) > diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h > index 0902a24..c1be305 100644 > --- a/target-lm32/cpu.h > +++ b/target-lm32/cpu.h > @@ -184,6 +184,7 @@ typedef struct CPULM32State { >=20 > } CPULM32State; >=20 > +#include "cpu-qom.h" >=20 > CPULM32State *cpu_lm32_init(const char *cpu_model); > void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf); > diff --git a/target-lm32/helper.c b/target-lm32/helper.c > index 5db8f8d..e89cc0e 100644 > --- a/target-lm32/helper.c > +++ b/target-lm32/helper.c > @@ -80,139 +80,57 @@ void do_interrupt(CPULM32State *env) > } > } >=20 > -typedef struct { > - const char *name; > - uint32_t revision; > - uint8_t num_interrupts; > - uint8_t num_breakpoints; > - uint8_t num_watchpoints; > - uint32_t features; > -} LM32Def; > +typedef struct LM32CPUListState { > + fprintf_function cpu_fprintf; > + FILE *file; > +} LM32CPUListState; >=20 > -static const LM32Def lm32_defs[] =3D { > - { > - .name =3D "lm32-basic", > - .revision =3D 3, > - .num_interrupts =3D 32, > - .num_breakpoints =3D 4, > - .num_watchpoints =3D 4, > - .features =3D (LM32_FEATURE_SHIFT > - | LM32_FEATURE_SIGN_EXTEND > - | LM32_FEATURE_CYCLE_COUNT), > - }, > - { > - .name =3D "lm32-standard", > - .revision =3D 3, > - .num_interrupts =3D 32, > - .num_breakpoints =3D 4, > - .num_watchpoints =3D 4, > - .features =3D (LM32_FEATURE_MULTIPLY > - | LM32_FEATURE_DIVIDE > - | LM32_FEATURE_SHIFT > - | LM32_FEATURE_SIGN_EXTEND > - | LM32_FEATURE_I_CACHE > - | LM32_FEATURE_CYCLE_COUNT), > - }, > - { > - .name =3D "lm32-full", > - .revision =3D 3, > - .num_interrupts =3D 32, > - .num_breakpoints =3D 4, > - .num_watchpoints =3D 4, > - .features =3D (LM32_FEATURE_MULTIPLY > - | LM32_FEATURE_DIVIDE > - | LM32_FEATURE_SHIFT > - | LM32_FEATURE_SIGN_EXTEND > - | LM32_FEATURE_I_CACHE > - | LM32_FEATURE_D_CACHE > - | LM32_FEATURE_CYCLE_COUNT), > - } > -}; > - > -void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf) > +/* Sort alphabetically. */ > +static gint lm32_cpu_list_compare(gconstpointer a, gconstpointer b) > { > - int i; > + ObjectClass *class_a =3D OBJECT_CLASS(a); > + ObjectClass *class_b =3D OBJECT_CLASS(b); >=20 > - cpu_fprintf(f, "Available CPUs:\n"); > - for (i =3D 0; i < ARRAY_SIZE(lm32_defs); i++) { > - cpu_fprintf(f, " %s\n", lm32_defs[i].name); > - } > + return strcasecmp(object_class_get_name(class_a), > + object_class_get_name(class_b)); > } >=20 > -static const LM32Def *cpu_lm32_find_by_name(const char *name) > +static void lm32_cpu_list_entry(gpointer data, gpointer user_data) > { > - int i; > - > - for (i =3D 0; i < ARRAY_SIZE(lm32_defs); i++) { > - if (strcasecmp(name, lm32_defs[i].name) =3D=3D 0) { > - return &lm32_defs[i]; > - } > - } > + ObjectClass *klass =3D data; > + LM32CPUListState *s =3D user_data; >=20 > - return NULL; > + (*s->cpu_fprintf)(s->file, " %s\n", > + object_class_get_name(klass)); > } >=20 > -static uint32_t cfg_by_def(const LM32Def *def) > +void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf) > { > - uint32_t cfg =3D 0; > - > - if (def->features & LM32_FEATURE_MULTIPLY) { > - cfg |=3D CFG_M; > - } > + LM32CPUListState s =3D { > + .file =3D f, > + .cpu_fprintf =3D cpu_fprintf, > + }; > + GSList *list; >=20 > - if (def->features & LM32_FEATURE_DIVIDE) { > - cfg |=3D CFG_D; > - } > - > - if (def->features & LM32_FEATURE_SHIFT) { > - cfg |=3D CFG_S; > - } > - > - if (def->features & LM32_FEATURE_SIGN_EXTEND) { > - cfg |=3D CFG_X; > - } > - > - if (def->features & LM32_FEATURE_I_CACHE) { > - cfg |=3D CFG_IC; > - } > - > - if (def->features & LM32_FEATURE_D_CACHE) { > - cfg |=3D CFG_DC; > - } > - > - if (def->features & LM32_FEATURE_CYCLE_COUNT) { > - cfg |=3D CFG_CC; > - } > - > - cfg |=3D (def->num_interrupts << CFG_INT_SHIFT); > - cfg |=3D (def->num_breakpoints << CFG_BP_SHIFT); > - cfg |=3D (def->num_watchpoints << CFG_WP_SHIFT); > - cfg |=3D (def->revision << CFG_REV_SHIFT); > - > - return cfg; > + list =3D object_class_get_list(TYPE_LM32_CPU, false); > + list =3D g_slist_sort(list, lm32_cpu_list_compare); > + cpu_fprintf(f, "Available CPUs:\n"); > + g_slist_foreach(list, lm32_cpu_list_entry, &s); > + g_slist_free(list); > } >=20 > CPULM32State *cpu_lm32_init(const char *cpu_model) > { > + LM32CPU *cpu; > CPULM32State *env; > - const LM32Def *def; > static int tcg_initialized; >=20 > - def =3D cpu_lm32_find_by_name(cpu_model); > - if (!def) { > + if (object_class_by_name(cpu_model) =3D=3D NULL) { > return NULL; > } > + cpu =3D LM32_CPU(object_new(cpu_model)); > + env =3D &cpu->env; >=20 > - env =3D g_malloc0(sizeof(CPULM32State)); > - > - env->features =3D def->features; > - env->num_bps =3D def->num_breakpoints; > - env->num_wps =3D def->num_watchpoints; > - env->cfg =3D cfg_by_def(def); > - env->flags =3D 0; > - > - cpu_exec_init(env); > - cpu_state_reset(env); > qemu_init_vcpu(env); >=20 > if (!tcg_initialized) { =2D-=20 Michael