Re: [PATCH 06/25] drm/i915: add ValleyView registers, stub code, and watermark support

[Daniel Vetter <daniel@ffwll.ch>]

On Wed, Mar 21, 2012 at 12:48:27PM -0700, Jesse Barnes wrote:
> ValleyView is a CedarView-like chip but with an Ivybridge graphics core.
> This patch adds initial framework for supporting this chip.
> 
> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/i915_drv.c      |   21 +++++++++
>  drivers/gpu/drm/i915/i915_drv.h      |    2 +
>  drivers/gpu/drm/i915/i915_reg.h      |   59 ++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_display.c |   82 +++++++++++++++++++++++++++++++++-
>  4 files changed, 163 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 06533cb..b83a0dc 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -248,6 +248,24 @@ static const struct intel_device_info intel_ivybridge_m_info = {
>  	.has_llc = 1,
>  };
>  
> +static const struct intel_device_info intel_valleyview_m_info = {
> +	.gen = 7, .is_mobile = 1,
> +	.need_gfx_hws = 1, .has_hotplug = 1,
> +	.has_fbc = 0,
> +	.has_bsd_ring = 1,
> +	.has_blt_ring = 1,
> +	.is_valleyview = 1,
> +};
> +
> +static const struct intel_device_info intel_valleyview_d_info = {
> +	.gen = 7, .is_mobile = 1,
> +	.need_gfx_hws = 1, .has_hotplug = 1,
> +	.has_fbc = 0,
> +	.has_bsd_ring = 1,
> +	.has_blt_ring = 1,
> +	.is_valleyview = 1,
> +};
> +
>  static const struct pci_device_id pciidlist[] = {		/* aka */
>  	INTEL_VGA_DEVICE(0x3577, &intel_i830_info),		/* I830_M */
>  	INTEL_VGA_DEVICE(0x2562, &intel_845g_info),		/* 845_G */
> @@ -292,6 +310,9 @@ static const struct pci_device_id pciidlist[] = {		/* aka */
>  	INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
>  	INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
>  	INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
> +	INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
> +	INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
> +	INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),

This should be in the last patch.

>  	{0, 0, 0}
>  };
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0294330..2b8b32d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -255,6 +255,7 @@ struct intel_device_info {
>  	u8 is_broadwater:1;
>  	u8 is_crestline:1;
>  	u8 is_ivybridge:1;
> +	u8 is_valleyview:1;
>  	u8 has_fbc:1;
>  	u8 has_pipe_cxsr:1;
>  	u8 has_hotplug:1;
> @@ -1005,6 +1006,7 @@ struct drm_i915_file_private {
>  #define IS_IRONLAKE_D(dev)	((dev)->pci_device == 0x0042)
>  #define IS_IRONLAKE_M(dev)	((dev)->pci_device == 0x0046)
>  #define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)
> +#define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
>  #define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
>  
>  /*
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ad6b5e0..7d33c49 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -851,8 +851,11 @@
>  #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
>  #define   DPLL_VCO_ENABLE		(1 << 31)
>  #define   DPLL_DVO_HIGH_SPEED		(1 << 30)
> +#define   DPLL_EXT_BUFFER_ENABLE	(1 << 30) /* VLV */
>  #define   DPLL_SYNCLOCK_ENABLE		(1 << 29)
> +#define   DPLL_REFA_CLK_ENABLE		(1 << 29) /* VLV */
>  #define   DPLL_VGA_MODE_DIS		(1 << 28)
> +#define   DPLL_DUAL_PIPE		(1 << 26) /* VLV */

Please postfix VLV bits with _VLV. Afaics new bits in an existing reg are
postfixed with the marketing name/gen/codename of the chip that introduced
them. New regs that fit into existing register blocks are also postfixed.
Completely new regs are usually prefixed.

More of these below.

>  #define   DPLLB_MODE_DAC_SERIAL		(1 << 26) /* i915 */
>  #define   DPLLB_MODE_LVDS		(2 << 26) /* i915 */
>  #define   DPLL_MODE_MASK		(3 << 26)
> @@ -863,6 +866,9 @@
>  #define   DPLL_P2_CLOCK_DIV_MASK	0x03000000 /* i915 */
>  #define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
>  #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */
> +#define   DPLL_VOLTAGE_LDO		(1<<14)
> +#define   DPLL_INTEGRATED_CLOCK		(1<<13)
> +#define   DPLL_RATE_SWITCH		(1<<8)
>  
>  #define SRX_INDEX		0x3c4
>  #define SRX_DATA		0x3c5
> @@ -958,6 +964,9 @@
>  #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
>  #define _DPLL_B_MD 0x06020 /* 965+ only */
>  #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
> +
> +#define RAWCLK_FREQ			0x6024 /* VLV */
> +
>  #define _FPA0	0x06040
>  #define _FPA1	0x06044
>  #define _FPB0	0x06048
> @@ -1098,6 +1107,12 @@
>  #define RAMCLK_GATE_D		0x6210		/* CRL only */
>  #define DEUC			0x6214          /* CRL only */
>  
> +#define FW_BLC_SELF_VLV		0x6500
> +#define  FW_CSPWRDWNEN		(1<<15)
> +#define MI_ARB_VLV		0x6504
> +#define  DISP_TRICKLE_FEED_DIS	(1<<2)
> +#define CZCLK_CDCLK_FREQ_RATIO	0x6508
> +
>  /*
>   * Palette regs
>   */
> @@ -2475,23 +2490,30 @@
>  #define   PIPECONF_DITHER_TYPE_TEMP (3<<2)
>  #define _PIPEASTAT		0x70024
>  #define   PIPE_FIFO_UNDERRUN_STATUS		(1UL<<31)
> +#define   SPRITE1_FLIPDONE_INT_EN		(1UL<<30) /* VLV only; typo, should be status? */
>  #define   PIPE_CRC_ERROR_ENABLE			(1UL<<29)
>  #define   PIPE_CRC_DONE_ENABLE			(1UL<<28)
>  #define   PIPE_GMBUS_EVENT_ENABLE		(1UL<<27)
> +#define   PLANE_FLIP_DONE_INT_EN		(1UL<<26) /* VLV only, ?? */
>  #define   PIPE_HOTPLUG_INTERRUPT_ENABLE		(1UL<<26)
>  #define   PIPE_VSYNC_INTERRUPT_ENABLE		(1UL<<25)
>  #define   PIPE_DISPLAY_LINE_COMPARE_ENABLE	(1UL<<24)
>  #define   PIPE_DPST_EVENT_ENABLE		(1UL<<23)
> +#define   SPRITE0_FLIP_DONE_INT_EN		(1UL<<26) /* VLV only, ?? */
>  #define   PIPE_LEGACY_BLC_EVENT_ENABLE		(1UL<<22)
>  #define   PIPE_ODD_FIELD_INTERRUPT_ENABLE	(1UL<<21)
>  #define   PIPE_EVEN_FIELD_INTERRUPT_ENABLE	(1UL<<20)
>  #define   PIPE_HOTPLUG_TV_INTERRUPT_ENABLE	(1UL<<18) /* pre-965 */
>  #define   PIPE_START_VBLANK_INTERRUPT_ENABLE	(1UL<<18) /* 965 or later */
>  #define   PIPE_VBLANK_INTERRUPT_ENABLE		(1UL<<17)
> +#define   PIPEA_HBLANK_INT_EN			(1UL<<16) /* VLV only, ?? */
>  #define   PIPE_OVERLAY_UPDATED_ENABLE		(1UL<<16)
> +#define   SPRITE1_FLIPDONE_INT_STATUS		(1UL<<15) /* VLV only */
> +#define   SPRITE0_FLIPDONE_INT_STATUS		(1UL<<15) /* VLV only */
>  #define   PIPE_CRC_ERROR_INTERRUPT_STATUS	(1UL<<13)
>  #define   PIPE_CRC_DONE_INTERRUPT_STATUS	(1UL<<12)
>  #define   PIPE_GMBUS_INTERRUPT_STATUS		(1UL<<11)
> +#define   PLANE_FLIPDONE_INT_STATUS		(1UL<<10) /* VLV only */
>  #define   PIPE_HOTPLUG_INTERRUPT_STATUS		(1UL<<10)
>  #define   PIPE_VSYNC_INTERRUPT_STATUS		(1UL<<9)
>  #define   PIPE_DISPLAY_LINE_COMPARE_STATUS	(1UL<<8)
> @@ -2516,6 +2538,40 @@
>  #define PIPEFRAMEPIXEL(pipe)  _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
>  #define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
>  
> +#define DPFLIPSTAT				0x70028 /* VLV only */
> +#define   PIPEB_LINE_COMPARE_STATUS		(1<<29)
> +#define   PIPEB_HLINE_INT_EN			(1<<28)
> +#define   PIPEB_VBLANK_INT_EN			(1<<27)
> +#define   SPRITED_FLIPDONE_INT_EN		(1<<26)
> +#define   SPRITEC_FLIPDONE_INT_EN		(1<<25)
> +#define   PLANEB_FLIPDONE_INT_EN		(1<<24)
> +#define   PIPEA_LINE_COMPARE_STATUS		(1<<21)
> +#define   PIPEA_HLINE_INT_EN			(1<<20)
> +#define   PIPEA_VBLANK_INT_EN			(1<<19)
> +#define   SPRITEB_FLIPDONE_INT_EN		(1<<18)
> +#define   SPRITEA_FLIPDONE_INT_EN		(1<<17)
> +#define   PLANEA_FLIPDONE_INT_EN		(1<<16)
> +
> +#define DPINVGTT				0x7002c /* VLV only */
> +#define   CURSORB_INVALID_GTT_INT_EN		(1<<23)
> +#define   CURSORA_INVALID_GTT_INT_EN		(1<<22)
> +#define   SPRITED_INVALID_GTT_INT_EN		(1<<21)
> +#define   SPRITEC_INVALID_GTT_INT_EN		(1<<20)
> +#define   PLANEB_INVALID_GTT_INT_EN		(1<<19)
> +#define   SPRITEB_INVALID_GTT_INT_EN		(1<<18)
> +#define   SPRITEA_INVALID_GTT_INT_EN		(1<<17)
> +#define   PLANEA_INVALID_GTT_INT_EN		(1<<16)
> +#define   DPINVGTT_EN_MASK			0xff0000
> +#define   CURSORB_INVALID_GTT_STATUS		(1<<7)
> +#define   CURSORA_INVALID_GTT_STATUS		(1<<6)
> +#define   SPRITED_INVALID_GTT_STATUS		(1<<5)
> +#define   SPRITEC_INVALID_GTT_STATUS		(1<<4)
> +#define   PLANEB_INVALID_GTT_STATUS		(1<<3)
> +#define   SPRITEB_INVALID_GTT_STATUS		(1<<2)
> +#define   SPRITEA_INVALID_GTT_STATUS		(1<<1)
> +#define   PLANEA_INVALID_GTT_STATUS		(1<<0)
> +#define   DPINVGTT_STATUS_MASK			0xff
> +
>  #define DSPARB			0x70030
>  #define   DSPARB_CSTART_MASK	(0x7f << 7)
>  #define   DSPARB_CSTART_SHIFT	7
> @@ -2550,6 +2606,7 @@
>  #define I915_FIFO_LINE_SIZE	64
>  #define I830_FIFO_LINE_SIZE	32
>  
> +#define VALLEYVIEW_FIFO_SIZE	255
>  #define G4X_FIFO_SIZE		127
>  #define I965_FIFO_SIZE		512
>  #define I945_FIFO_SIZE		127
> @@ -2557,6 +2614,7 @@
>  #define I855GM_FIFO_SIZE	127 /* In cachelines */
>  #define I830_FIFO_SIZE		95
>  
> +#define VALLEYVIEW_MAX_WM	0xff
>  #define G4X_MAX_WM		0x3f
>  #define I915_MAX_WM		0x3f
>  
> @@ -2571,6 +2629,7 @@
>  #define PINEVIEW_CURSOR_DFT_WM	0
>  #define PINEVIEW_CURSOR_GUARD_WM	5
>  
> +#define VALLEYVIEW_CURSOR_MAX_WM 64
>  #define I965_CURSOR_FIFO	64
>  #define I965_CURSOR_MAX_WM	32
>  #define I965_CURSOR_DFT_WM	8

Imo the watermark, clock speed and clock gating code below would look good
in a separate patch ;-) You're already overflowing the subject of this one
here.

> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b8daeef..084e154 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3530,6 +3530,11 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
>  	return true;
>  }
>  
> +static int valleyview_get_display_clock_speed(struct drm_device *dev)
> +{
> +	return 400000; /* FIXME */
> +}
> +
>  static int i945_get_display_clock_speed(struct drm_device *dev)
>  {
>  	return 400000;
> @@ -3679,6 +3684,20 @@ static const struct intel_watermark_params g4x_cursor_wm_info = {
>  	2,
>  	G4X_FIFO_LINE_SIZE,
>  };
> +static const struct intel_watermark_params valleyview_wm_info = {
> +	VALLEYVIEW_FIFO_SIZE,
> +	VALLEYVIEW_MAX_WM,
> +	VALLEYVIEW_MAX_WM,
> +	2,
> +	G4X_FIFO_LINE_SIZE,
> +};
> +static const struct intel_watermark_params valleyview_cursor_wm_info = {
> +	I965_CURSOR_FIFO,
> +	VALLEYVIEW_CURSOR_MAX_WM,
> +	I965_CURSOR_DFT_WM,
> +	2,
> +	G4X_FIFO_LINE_SIZE,
> +};
>  static const struct intel_watermark_params i965_cursor_wm_info = {
>  	I965_CURSOR_FIFO,
>  	I965_CURSOR_MAX_WM,
> @@ -4203,6 +4222,55 @@ static bool g4x_compute_srwm(struct drm_device *dev,
>  
>  #define single_plane_enabled(mask) is_power_of_2(mask)
>  
> +static void valleyview_update_wm(struct drm_device *dev)
> +{
> +	static const int sr_latency_ns = 12000;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
> +	int plane_sr, cursor_sr;
> +	unsigned int enabled = 0;
> +
> +	if (g4x_compute_wm0(dev, 0,
> +			    &valleyview_wm_info, latency_ns,
> +			    &valleyview_cursor_wm_info, latency_ns,
> +			    &planea_wm, &cursora_wm))
> +		enabled |= 1;
> +
> +	if (g4x_compute_wm0(dev, 1,
> +			    &valleyview_wm_info, latency_ns,
> +			    &valleyview_cursor_wm_info, latency_ns,
> +			    &planeb_wm, &cursorb_wm))
> +		enabled |= 2;
> +
> +	plane_sr = cursor_sr = 0;
> +	if (single_plane_enabled(enabled) &&
> +	    g4x_compute_srwm(dev, ffs(enabled) - 1,
> +			     sr_latency_ns,
> +			     &valleyview_wm_info,
> +			     &valleyview_cursor_wm_info,
> +			     &plane_sr, &cursor_sr))
> +		I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
> +	else
> +		I915_WRITE(FW_BLC_SELF,
> +			   I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
> +
> +	DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
> +		      planea_wm, cursora_wm,
> +		      planeb_wm, cursorb_wm,
> +		      plane_sr, cursor_sr);
> +
> +	I915_WRITE(DSPFW1,
> +		   (plane_sr << DSPFW_SR_SHIFT) |
> +		   (cursorb_wm << DSPFW_CURSORB_SHIFT) |
> +		   (planeb_wm << DSPFW_PLANEB_SHIFT) |
> +		   planea_wm);
> +	I915_WRITE(DSPFW2,
> +		   (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
> +		   (cursora_wm << DSPFW_CURSORA_SHIFT));
> +	I915_WRITE(DSPFW3,
> +		   (I915_READ(DSPFW3) | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)));
> +}
> +
>  static void g4x_update_wm(struct drm_device *dev)
>  {
>  	static const int sr_latency_ns = 12000;
> @@ -8488,6 +8556,11 @@ void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
>  	mutex_unlock(&dev_priv->dev->struct_mutex);
>  }
>  
> +static void valleyview_init_clock_gating(struct drm_device *dev)
> +{
> +	return;
> +}
> +
>  static void ironlake_init_clock_gating(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -8895,7 +8968,10 @@ static void intel_init_display(struct drm_device *dev)
>  	}
>  
>  	/* Returns the core display clock speed */
> -	if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
> +	if (IS_VALLEYVIEW(dev))
> +		dev_priv->display.get_display_clock_speed =
> +			valleyview_get_display_clock_speed;
> +	else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
>  		dev_priv->display.get_display_clock_speed =
>  			i945_get_display_clock_speed;
>  	else if (IS_I915G(dev))
> @@ -8990,6 +9066,10 @@ static void intel_init_display(struct drm_device *dev)
>  			dev_priv->display.write_eld = ironlake_write_eld;
>  		} else
>  			dev_priv->display.update_wm = NULL;
> +	} else if (IS_VALLEYVIEW(dev)) {
> +		dev_priv->display.update_wm = valleyview_update_wm;
> +		dev_priv->display.init_clock_gating =
> +			valleyview_init_clock_gating;
>  	} else if (IS_PINEVIEW(dev)) {
>  		if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
>  					    dev_priv->is_ddr3,
> -- 
> 1.7.5.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48