[RFC] [PATCH 00/38] Haswell

[RFC] [PATCH 00/38] Haswell

[Eugeni Dodonov]

Hi folks,

To contribute to everyones curiosity and further enrich Phoronix articles
:), this is the initial Haswell enablement patchset for basic modesetting
support over VGA.

This is actually the first time I am doing such enablement, and the
combination of HSW/LPT changes proved to be quite tricky, yet also very cool
to do. But certainly, while I tried to split the patches in the best way to
'tell a story', I suspect lots and lots of things could be improved. So
bikeshedding is much welcomed! And of course, there are still a bunch of
things missing, but those can be done in parallel now.

As for those patches, I organized them in the following way:
 - The first part adds new hardware information and new registers which we'll
   need to make it work (a.k.a, 'The Pledge'). This goes from patch 01 until
   patch 21.
 - The second part does small changes to existent functions to make them work
   on Haswell ('The Turn'). This goes from patch 22 to patch 28.  Haswell is
   not quite Gen7, but is shares lots of stuff with what we already have, so
   there was no point in reinventing the wheel just now.
 - The third part makes things work by enabling power wells, DDI and FDI
   connections, PCH-specific stuff and so on ('The Prestige'). This is from
   patch 29 to patch 35. Those are the scariest ones, but I couldn't split them
   better and still maintain logical consistency among them.  Initially, those
   were 24 small patches, but it was very hard to keep track of them, so I
   combined them into just 6 for this patchset.
 - And finally, there are 2 last patches ('The Prestige Debug' :)) which won't
   be present in the final series, but are helpful at least for me to trace
   where things go wrong. So if you run into issues and want to send me a
   dmesg, those traces will make my life so much easier.

I didn't wanted to go much deeper with HSW for now because I would end up
doing a massive code reordering to maintain my mental sanity, and as we
already discussed by email earlier today Jesse is running into same problems
as well. So perhaps we should just settle on doing some cleanup in our
intel_display module before adding more platform-specific stuff?


And finally, I'd like to thank once again Jesse with his help on some of the
trickiest issues, and Ben for taking a look at those patches and point me at
things I've been doing wrong :).


Cheers,
Eugeni



Eugeni Dodonov (37):
  drm/i915: add Haswell devices and their PCI IDs
  drm/i915: add support for LynxPoint PCH
  drm/i915: add HAS_PLL_SPLIT macro
  drm/i915: add haswell into the PCH SPLIT company
  drm/i915: add support for power wells
  drm/i915: add DDI registers
  drm/i915: add DP_TP_CTL registers
  drm/i915: add DP_TP_STATUS registers
  drm/i915: add definitions for DDI_BUF_CTL registers
  drm/i915: add definition of LPT FDI port width registers
  drm/i915: add definition of DDI buffer translations regs
  drm/i915: add SBI registers
  drm/i915: add support for SBI ops
  drm/i915: add PIXCLK_GATE register
  drm/i915: add S PLL control
  drm/i915: add port clock selection support for HSW
  drm/i915: add SSC offsets for SBI access
  drm/i915: add GTC registers
  drm/i915: add LCPLL control registers
  drm/i915: add WM_LINETIME registers
  drm/i915: calculate watermarks on Gen7 archs in one place
  drm/i915: program WM_LINETIME on Haswell
  drm/i915: do not set 6BPP dithering on haswell
  drm/i915: share forcewaking code between IVB and HSW
  drm/i915: haswell has 3 pipes as well
  drm/i915: reuse Ivybridge interrupts code for Haswell
  drm/i915: share pipe count handling with Ivybridge
  drm/i915: share IVB cursor routine with Haswell
  drm/i915: enable power wells on haswell init
  drm/i915: disable rc6 on haswell for now
  drm/i915: enable PCH earlier
  drm/i915: perform Haswell DDI link training in FDI mode
  drm/i915: double-write DDI translation table
  drm/i915: do not use fdi_normal_train on haswell
  drm/i915: program iCLKIP on Lynx Point
  drm/i915: add warning when using old bits on Haswell/LPT
  drm/i915: dump registers read/write ops

 drivers/char/agp/intel-agp.c         |    4 +
 drivers/char/agp/intel-agp.h         |   11 +
 drivers/char/agp/intel-gtt.c         |   14 +
 drivers/gpu/drm/i915/i915_dma.c      |    2 +-
 drivers/gpu/drm/i915/i915_drv.c      |   29 ++
 drivers/gpu/drm/i915/i915_drv.h      |    7 +-
 drivers/gpu/drm/i915/i915_irq.c      |    6 +-
 drivers/gpu/drm/i915/i915_reg.h      |  181 ++++++++++
 drivers/gpu/drm/i915/intel_display.c |  656 ++++++++++++++++++++++++++++++++--
 9 files changed, 883 insertions(+), 27 deletions(-)

-- 
1.7.9.2

[PATCH 01/37] drm/i915: add Haswell devices and their PCI IDs

[Eugeni Dodonov]

This adds product definitions for desktop, mobile and server boards.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/char/agp/intel-agp.c    |    4 ++++
 drivers/char/agp/intel-agp.h    |   11 +++++++++++
 drivers/char/agp/intel-gtt.c    |   14 ++++++++++++++
 drivers/gpu/drm/i915/i915_drv.c |   23 +++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h |    2 ++
 5 files changed, 54 insertions(+)

diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index 962e75d..0ad4933 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -907,6 +907,10 @@ static struct pci_device_id agp_intel_pci_table[] = {
 	ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB),
 	ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB),
 	ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB),
+	ID(PCI_DEVICE_ID_INTEL_HASWELL_HB),
+	ID(PCI_DEVICE_ID_INTEL_HASWELL_M_HB),
+	ID(PCI_DEVICE_ID_INTEL_HASWELL_S_HB),
+	ID(PCI_DEVICE_ID_INTEL_HASWELL_E_HB),
 	{ }
 };
 
diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
index 5da67f1..46394c11 100644
--- a/drivers/char/agp/intel-agp.h
+++ b/drivers/char/agp/intel-agp.h
@@ -234,6 +234,17 @@
 #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG		0x0166
 #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB		0x0158  /* Server */
 #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG		0x015A
+#define PCI_DEVICE_ID_INTEL_HASWELL_HB				0x0400 /* Desktop */
+#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG		0x0402
+#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG		0x0412
+#define PCI_DEVICE_ID_INTEL_HASWELL_M_HB			0x0404 /* Mobile */
+#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG		0x0406
+#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG		0x0416
+#define PCI_DEVICE_ID_INTEL_HASWELL_S_HB			0x0408 /* Server */
+#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG		0x040a
+#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG		0x041a
+#define PCI_DEVICE_ID_INTEL_HASWELL_SDV		0x0c16 /* SDV */
+#define PCI_DEVICE_ID_INTEL_HASWELL_E_HB			0x0c04
 
 int intel_gmch_probe(struct pci_dev *pdev,
 			       struct agp_bridge_data *bridge);
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 5cf47ac..f494556 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1459,6 +1459,20 @@ static const struct intel_gtt_driver_description {
 	    "Ivybridge", &sandybridge_gtt_driver },
 	{ PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG,
 	    "Ivybridge", &sandybridge_gtt_driver },
+	{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG,
+	    "Haswell", &sandybridge_gtt_driver },
+	{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG,
+	    "Haswell", &sandybridge_gtt_driver },
+	{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG,
+	    "Haswell", &sandybridge_gtt_driver },
+	{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG,
+	    "Haswell", &sandybridge_gtt_driver },
+	{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG,
+	    "Haswell", &sandybridge_gtt_driver },
+	{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG,
+	    "Haswell", &sandybridge_gtt_driver },
+	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV,
+	    "Haswell", &sandybridge_gtt_driver },
 	{ 0, NULL, NULL }
 };
 
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 0694e17..d4f542b 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -248,6 +248,22 @@ static const struct intel_device_info intel_ivybridge_m_info = {
 	.has_llc = 1,
 };
 
+static const struct intel_device_info intel_haswell_d_info = {
+	.is_haswell = 1, .gen = 7,
+	.need_gfx_hws = 1, .has_hotplug = 1,
+	.has_bsd_ring = 1,
+	.has_blt_ring = 1,
+	.has_llc = 1,
+};
+
+static const struct intel_device_info intel_haswell_m_info = {
+	.is_haswell = 1, .gen = 7, .is_mobile = 1,
+	.need_gfx_hws = 1, .has_hotplug = 1,
+	.has_bsd_ring = 1,
+	.has_blt_ring = 1,
+	.has_llc = 1,
+};
+
 static const struct pci_device_id pciidlist[] = {		/* aka */
 	INTEL_VGA_DEVICE(0x3577, &intel_i830_info),		/* I830_M */
 	INTEL_VGA_DEVICE(0x2562, &intel_845g_info),		/* 845_G */
@@ -292,6 +308,13 @@ static const struct pci_device_id pciidlist[] = {		/* aka */
 	INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 	INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 	INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
+	INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
+	INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
+	INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
+	INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
+	INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
+	INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
+	INTEL_VGA_DEVICE(0x0c16, &intel_haswell_d_info), /* SDV */
 	{0, 0, 0}
 };
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c0f19f5..9a99ef1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -255,6 +255,7 @@ struct intel_device_info {
 	u8 is_broadwater:1;
 	u8 is_crestline:1;
 	u8 is_ivybridge:1;
+	u8 is_haswell:1;
 	u8 has_fbc:1;
 	u8 has_pipe_cxsr:1;
 	u8 has_hotplug:1;
@@ -1001,6 +1002,7 @@ struct drm_i915_file_private {
 #define IS_IRONLAKE_D(dev)	((dev)->pci_device == 0x0042)
 #define IS_IRONLAKE_M(dev)	((dev)->pci_device == 0x0046)
 #define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)
+#define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
 #define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
 
 /*
-- 
1.7.9.2

[PATCH 02/37] drm/i915: add support for LynxPoint PCH

[Eugeni Dodonov]

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c |    4 ++++
 drivers/gpu/drm/i915/i915_drv.h |    2 ++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d4f542b..5fe9d62 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -326,6 +326,7 @@ MODULE_DEVICE_TABLE(pci, pciidlist);
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE	0x3b00
 #define INTEL_PCH_CPT_DEVICE_ID_TYPE	0x1c00
 #define INTEL_PCH_PPT_DEVICE_ID_TYPE	0x1e00
+#define INTEL_PCH_LPT_DEVICE_ID_TYPE	0x8c00
 
 void intel_detect_pch(struct drm_device *dev)
 {
@@ -354,6 +355,9 @@ void intel_detect_pch(struct drm_device *dev)
 				/* PantherPoint is CPT compatible */
 				dev_priv->pch_type = PCH_CPT;
 				DRM_DEBUG_KMS("Found PatherPoint PCH\n");
+			} else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
+				dev_priv->pch_type = PCH_LPT;
+				DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 			}
 		}
 		pci_dev_put(pch);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9a99ef1..49488e1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -292,6 +292,7 @@ enum no_fbc_reason {
 enum intel_pch {
 	PCH_IBX,	/* Ibexpeak PCH */
 	PCH_CPT,	/* Cougarpoint PCH */
+	PCH_LPT,	/* Lynxpoint PCH */
 };
 
 #define QUIRK_PIPEA_FORCE (1<<0)
@@ -1050,6 +1051,7 @@ struct drm_i915_file_private {
 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
 
 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
+#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
 
-- 
1.7.9.2

[PATCH 03/37] drm/i915: add HAS_PLL_SPLIT macro

[Eugeni Dodonov]

Ivy Bridge is the only GPU which has split 3-display support over 2 PLLs.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h |    1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 49488e1..fb50c42 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1048,6 +1048,7 @@ struct drm_i915_file_private {
 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
 
 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
+#define HAS_PLL_SPLIT(dev) (IS_IVYBRIDGE(dev))
 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
 
 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
-- 
1.7.9.2

[PATCH 04/37] drm/i915: add haswell into the PCH SPLIT company

[Eugeni Dodonov]

Haswell is similar to Ivy Bridge in this sense.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fb50c42..51e04ec 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1047,7 +1047,7 @@ struct drm_i915_file_private {
 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
 
-#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
+#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
 #define HAS_PLL_SPLIT(dev) (IS_IVYBRIDGE(dev))
 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
 
-- 
1.7.9.2

[PATCH 05/37] drm/i915: add support for power wells

[Eugeni Dodonov]

This defines the registers used by different power wells.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |   13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 52a06be..ddc9c87 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3850,4 +3850,17 @@
 #define   AUD_CONFIG_PIXEL_CLOCK_HDMI		(0xf << 16)
 #define   AUD_CONFIG_DISABLE_NCTS		(1 << 3)
 
+/* HSW Power Wells */
+#define HSW_PWR_WELL_CTL1		0x45400		/* BIOS */
+#define HSW_PWR_WELL_CTL2		0x45404		/* Driver */
+#define HSW_PWR_WELL_CTL3		0x45408		/* KVMR */
+#define HSW_PWR_WELL_CTL4		0x4540C		/* Debug */
+#define   HSW_PWR_WELL_ENABLE	(1<<31)
+#define   HSW_PWR_WELL_STATE	(1<<30)
+#define HSW_PWR_WELL_CTL5		0x45410
+#define   HSW_PWR_WELL_ENABLE_SINGLE_STEP	(1<<31)
+#define   HSW_PWR_WELL_PWR_GATE_OVERRIDE	(1<<20)
+#define   HSW_PWR_WELL_FORCE_ON	(1<<19)
+#define HSW_PWR_WELL_CTL6		0x45414
+
 #endif /* _I915_REG_H_ */
-- 
1.7.9.2

[PATCH 06/37] drm/i915: add DDI registers

[Eugeni Dodonov]

There is one set of such registers for each pipe (A/B/C/EDP).

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |   27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ddc9c87..09b2267 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3863,4 +3863,31 @@
 #define   HSW_PWR_WELL_FORCE_ON	(1<<19)
 #define HSW_PWR_WELL_CTL6		0x45414
 
+/* Per-pipe DDI Function Control */
+#define PIPE_DDI_FUNC_CTL_A			0x60400
+#define PIPE_DDI_FUNC_CTL_B			0x61400
+#define PIPE_DDI_FUNC_CTL_C			0x62400
+#define PIPE_DDI_FUNC_CTL_EDP		0x6F400
+#define DDI_FUNC_CTL(pipe) _PIPE(pipe, \
+					PIPE_DDI_FUNC_CTL_A, \
+					PIPE_DDI_FUNC_CTL_B)
+#define  PIPE_DDI_FUNC_ENABLE		(1<<31)
+/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
+#define  PIPE_DDI_SELECT_DDI_B	(0x1<<28)
+#define  PIPE_DDI_SELECT_DDI_C	(0x2<<28)
+#define  PIPE_DDI_SELECT_DDI_D	(0x3<<28)
+#define  PIPE_DDI_SELECT_DDI_E	(0x4<<28)
+#define  PIPE_DDI_MODE_SELECT_HDMI	(0<<24)
+#define  PIPE_DDI_MODE_SELECT_DVI	(1<<24)
+#define  PIPE_DDI_MODE_SELECT_DP_SST	(2<<24)
+#define  PIPE_DDI_MODE_SELECT_FDI	(4<<24)
+#define  PIPE_DDI_BPC_8				(0<<20)
+#define  PIPE_DDI_BPC_10			(1<<20)
+#define  PIPE_DDI_BPC_6				(2<<20)
+#define  PIPE_DDI_BPC_12			(3<<20)
+#define  PIPE_DDI_BFI_ENABLE		(1<<4)
+#define  PIPE_DDI_PORT_WIDTH_X1			(0<<1)
+#define  PIPE_DDI_PORT_WIDTH_X2			(1<<1)
+#define  PIPE_DDI_PORT_WIDTH_X4			(3<<1)
+
 #endif /* _I915_REG_H_ */
-- 
1.7.9.2

[PATCH 07/37] drm/i915: add DP_TP_CTL registers

[Eugeni Dodonov]

This is one set of those registers for each pipe.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |   16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 09b2267..7a9232e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3890,4 +3890,20 @@
 #define  PIPE_DDI_PORT_WIDTH_X2			(1<<1)
 #define  PIPE_DDI_PORT_WIDTH_X4			(3<<1)
 
+/* DisplayPort Transport Control */
+#define DP_TP_CTL_A			0x64040
+#define DP_TP_CTL_B			0x64140
+#define DP_TP_CTL_C			0x64240
+#define DP_TP_CTL_D			0x64340
+#define DP_TP_CTL_E			0x64440
+#define  DP_TP_CTL_ENABLE		(1<<31)
+#define  DP_TP_CTL_MODE_SST	(0<<27)
+#define  DP_TP_CTL_MODE_MST	(1<<27)
+#define  DP_TP_CTL_ENHANCED_FRAME_ENABLE	(1<<18)
+#define  DP_TP_CTL_FDI_AUTOTRAIN	(1<<15)
+#define  DP_TP_CTL_LINK_TRAIN_MASK		(7<<8)
+#define  DP_TP_CTL_LINK_TRAIN_PAT1		(0<<8)
+#define  DP_TP_CTL_LINK_TRAIN_PAT2		(1<<8)
+#define  DP_TP_CTL_LINK_TRAIN_NORMAL	(3<<8)
+
 #endif /* _I915_REG_H_ */
-- 
1.7.9.2

[PATCH 08/37] drm/i915: add DP_TP_STATUS registers

[Eugeni Dodonov]

There is one set of those registers for each port.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7a9232e..3831fe7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3906,4 +3906,12 @@
 #define  DP_TP_CTL_LINK_TRAIN_PAT2		(1<<8)
 #define  DP_TP_CTL_LINK_TRAIN_NORMAL	(3<<8)
 
+/* DisplayPort Transport Status */
+#define DP_TP_STATUS_A			0x64044
+#define DP_TP_STATUS_B			0x64144
+#define DP_TP_STATUS_C			0x64244
+#define DP_TP_STATUS_D			0x64344
+#define DP_TP_STATUS_E			0x64444
+#define  DP_TP_STATUS_AUTOTRAIN_DONE	(1<<12)
+
 #endif /* _I915_REG_H_ */
-- 
1.7.9.2

[PATCH 09/37] drm/i915: add definitions for DDI_BUF_CTL registers

[Eugeni Dodonov]

There is one instance of those registers for each DDI port.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |   23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3831fe7..2927460 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3914,4 +3914,27 @@
 #define DP_TP_STATUS_E			0x64444
 #define  DP_TP_STATUS_AUTOTRAIN_DONE	(1<<12)
 
+/* DDI Buffer Control */
+#define DDI_BUF_CTL_A				0x64000
+#define DDI_BUF_CTL_B				0x64100
+#define DDI_BUF_CTL_C				0x64200
+#define DDI_BUF_CTL_D				0x64300
+#define DDI_BUF_CTL_E				0x64400
+#define  DDI_BUF_CTL_ENABLE			(1<<31)
+#define  DDI_BUF_EMP_400MV_0DB_HSW		(0<<24)   /* Sel0 */
+#define  DDI_BUF_EMP_400MV_3_5DB_HSW	(1<<24)   /* Sel1 */
+#define  DDI_BUF_EMP_400MV_6DB_HSW		(2<<24)   /* Sel2 */
+#define  DDI_BUF_EMP_400MV_9_5DB_HSW	(3<<24)   /* Sel3 */
+#define  DDI_BUF_EMP_600MV_0DB_HSW		(4<<24)   /* Sel4 */
+#define  DDI_BUF_EMP_600MV_3_5DB_HSW	(5<<24)   /* Sel5 */
+#define  DDI_BUF_EMP_600MV_6DB_HSW		(6<<24)   /* Sel6 */
+#define  DDI_BUF_EMP_800MV_0DB_HSW		(7<<24)   /* Sel7 */
+#define  DDI_BUF_EMP_800MV_3_5DB_HSW	(8<<24)   /* Sel8 */
+#define  DDI_BUF_EMP_MASK				(0xf<<24)
+#define  DDI_BUF_IS_IDLE				(1<<7)
+#define  DDI_PORT_WIDTH_X1				(0<<1)
+#define  DDI_PORT_WIDTH_X2				(1<<1)
+#define  DDI_PORT_WIDTH_X4				(3<<1)
+#define  DDI_INIT_DISPLAY_DETECTED		(1<<0)
+
 #endif /* _I915_REG_H_ */
-- 
1.7.9.2

[PATCH 10/37] drm/i915: add definition of LPT FDI port width registers

[Eugeni Dodonov]

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2927460..b732aa1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3473,6 +3473,9 @@
 #define  FDI_LINK_TRAIN_PATTERN_IDLE_CPT	(2<<8)
 #define  FDI_LINK_TRAIN_NORMAL_CPT		(3<<8)
 #define  FDI_LINK_TRAIN_PATTERN_MASK_CPT	(3<<8)
+/* LPT */
+#define  LPT_FDI_PORT_WIDTH_1X          (0<<19)
+#define  LPT_FDI_PORT_WIDTH_2X          (1<<19)
 
 #define _FDI_RXA_MISC            0xf0010
 #define _FDI_RXB_MISC            0xf1010
-- 
1.7.9.2

[PATCH 11/37] drm/i915: add definition of DDI buffer translations regs

[Eugeni Dodonov]

Those registers are used to train DDI buffer translations for each link
type.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b732aa1..0af47b4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3940,4 +3940,11 @@
 #define  DDI_PORT_WIDTH_X4				(3<<1)
 #define  DDI_INIT_DISPLAY_DETECTED		(1<<0)
 
+/* DDI Buffer Translations */
+#define DDI_BUF_TRANS_A				0x64E00
+#define DDI_BUF_TRANS_B				0x64E60
+#define DDI_BUF_TRANS_C				0x64EC0
+#define DDI_BUF_TRANS_D				0x64F20
+#define DDI_BUF_TRANS_E				0x64F80
+
 #endif /* _I915_REG_H_ */
-- 
1.7.9.2

[PATCH 12/37] drm/i915: add SBI registers

[Eugeni Dodonov]

Those are responsible for the Sideband Interface programming.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |   10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0af47b4..4ee8965 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3947,4 +3947,14 @@
 #define DDI_BUF_TRANS_D				0x64F20
 #define DDI_BUF_TRANS_E				0x64F80
 
+/* Sideband Interface (SBI) is programmed indirectly, via
+ * SBI_ADDR, which contains the register offset; and SBI_DATA,
+ * which contains the payload */
+#define SBI_ADDR				0xC6000
+#define SBI_DATA				0xC6004
+#define SBI_CTL_STAT			0xC6008
+#define  SBI_CTL_OP_CRRD		(0x6<<8)
+#define  SBI_CTL_OP_CRWR		(0x7<<8)
+#define  SBI_RESPONSE			(0x1<<1)
+#define  SBI_READY				(0x1<<0)
 #endif /* _I915_REG_H_ */
-- 
1.7.9.2

[PATCH 13/37] drm/i915: add support for SBI ops

[Eugeni Dodonov]

With Lynx Point, we need to use SBI to communicate with the display clock
control. This commit adds helper functions to access the registers via
SBI.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   44 ++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index de1ba19..c225de4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1198,6 +1198,50 @@ static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 	POSTING_READ(reg);
 }
 
+/* SBI access */
+static inline void
+SBI_WRITE(struct drm_i915_private *dev_priv, u16 reg, u32 value)
+{
+	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
+				10))
+		DRM_ERROR("timeout waiting for SBI to become ready\n");
+
+	I915_WRITE(SBI_ADDR,
+			(reg << 16));
+	I915_WRITE(SBI_DATA,
+			value);
+	I915_WRITE(SBI_CTL_STAT,
+			SBI_READY |
+			SBI_CTL_OP_CRWR);
+
+	if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE)) == 0,
+				10))
+		DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
+}
+
+static inline u32
+SBI_READ(struct drm_i915_private *dev_priv, u16 reg)
+{
+	u32 value;
+	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
+				10))
+		DRM_ERROR("timeout waiting for SBI to become ready\n");
+
+	I915_WRITE(SBI_ADDR,
+			(reg << 16));
+	I915_WRITE(SBI_CTL_STAT,
+			SBI_READY |
+			SBI_CTL_OP_CRRD);
+
+	if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE)) == 0,
+				10))
+		DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
+
+	value = I915_READ(SBI_DATA);
+
+	return value;
+}
+
 /**
  * intel_enable_pch_pll - enable PCH PLL
  * @dev_priv: i915 private structure
-- 
1.7.9.2

[PATCH 14/37] drm/i915: add PIXCLK_GATE register

[Eugeni Dodonov]

Pixel clock gating control for Lynx point.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |    6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4ee8965..9ff9856 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3957,4 +3957,10 @@
 #define  SBI_CTL_OP_CRWR		(0x7<<8)
 #define  SBI_RESPONSE			(0x1<<1)
 #define  SBI_READY				(0x1<<0)
+
+/* LPT PIXCLK_GATE */
+#define PIXCLK_GATE				0xC6020
+#define  PIXCLK_GATE_UNGATE		1<<0
+#define  PIXCLK_GATE_GATE		0<<0
+
 #endif /* _I915_REG_H_ */
-- 
1.7.9.2

[PATCH 15/37] drm/i915: add S PLL control

[Eugeni Dodonov]

This PLL control can drive DDI ports at desired frequencies for
DisplayPort and FDI connections.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9ff9856..e38dafc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3963,4 +3963,12 @@
 #define  PIXCLK_GATE_UNGATE		1<<0
 #define  PIXCLK_GATE_GATE		0<<0
 
+/* SPLL */
+#define SPLL_CTL				0x46020
+#define  SPLL_PLL_ENABLE		(1<<31)
+#define  SPLL_PLL_SCC			(1<<28)
+#define  SPLL_PLL_NON_SCC		(2<<28)
+#define  SPLL_PLL_FREQ_810MHz	(0<<26)
+#define  SPLL_PLL_FREQ_1350MHz	(1<<26)
+
 #endif /* _I915_REG_H_ */
-- 
1.7.9.2

[PATCH 16/37] drm/i915: add port clock selection support for HSW

[Eugeni Dodonov]

Multiple clocks can drive different outputs.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |   23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e38dafc..eebe9d3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3971,4 +3971,27 @@
 #define  SPLL_PLL_FREQ_810MHz	(0<<26)
 #define  SPLL_PLL_FREQ_1350MHz	(1<<26)
 
+/* Port clock selection */
+#define PORT_CLK_SEL_A			0x46100
+#define PORT_CLK_SEL_B			0x46104
+#define PORT_CLK_SEL_C			0x46108
+#define PORT_CLK_SEL_D			0x4610C
+#define PORT_CLK_SEL_E			0x46110
+#define  PORT_CLK_SEL_LCPLL_2700	(0<<29)
+#define  PORT_CLK_SEL_LCPLL_1350	(1<<29)
+#define  PORT_CLK_SEL_LCPLL_810		(2<<29)
+#define  PORT_CLK_SEL_SPLL			(3<<29)
+#define  PORT_CLK_SEL_WRPLL1		(4<<29)
+#define  PORT_CLK_SEL_WRPLL2		(5<<29)
+
+/* Pipe clock selection */
+#define PIPE_CLK_SEL_A			0x46140
+#define PIPE_CLK_SEL_B			0x46144
+#define PIPE_CLK_SEL(pipe) _PIPE(pipe, \
+					PIPE_CLK_SEL_A, \
+					PIPE_CLK_SEL_B)
+#define  PIPE_CLK_SEL_DDIB		(2<<29)
+#define  PIPE_CLK_SEL_DDIC		(3<<29)
+#define  PIPE_CLK_SEL_DDID		(4<<29)
+#define  PIPE_CLK_SEL_DDIE		(5<<29)
 #endif /* _I915_REG_H_ */
-- 
1.7.9.2

[PATCH 17/37] drm/i915: add SSC offsets for SBI access

[Eugeni Dodonov]

Different registers are identified by their target id and offset. To
simplify their programming, they are called as <RegisterName><TargetId>.
For example, SSCCTL register accessed through SBI at target id 6 and
offset 0c is called SBI_SSCCTL6.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |   15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eebe9d3..193fb11 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3958,6 +3958,21 @@
 #define  SBI_RESPONSE			(0x1<<1)
 #define  SBI_READY				(0x1<<0)
 
+/* SBI offsets */
+#define  SBI_SSCDIVINTPHASE6		0x0600
+#define   SBI_SSCDIVINTPHASE_DIVSEL_MASK	((0x7f)<<1)
+#define   SBI_SSCDIVINTPHASE_DIVSEL(x)		((x)<<1)
+#define   SBI_SSCDIVINTPHASE_INCVAL_MASK	((0x7f)<<8)
+#define   SBI_SSCDIVINTPHASE_INCVAL(x)		((x)<<8)
+#define   SBI_SSCDIVINTPHASE_DIR(x)			((x)<<15)
+#define   SBI_SSCDIVINTPHASE_PROPAGATE		(1<<0)
+#define  SBI_SSCCTL					0x020c
+#define  SBI_SSCCTL6				0x060C
+#define   SBI_SSCCTL_DISABLE		(1<<0)
+#define  SBI_SSCAUXDIV6				0x0610
+#define   SBI_SSCAUXDIV_FINALDIV2SEL(x)		((x)<<4)
+#define  SBI_DBUFF0					0x2a00
+
 /* LPT PIXCLK_GATE */
 #define PIXCLK_GATE				0xC6020
 #define  PIXCLK_GATE_UNGATE		1<<0
-- 
1.7.9.2

[PATCH 18/37] drm/i915: add GTC registers

[Eugeni Dodonov]

Add Global Time Clock registers

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |    5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 193fb11..03fb10d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4009,4 +4009,9 @@
 #define  PIPE_CLK_SEL_DDIC		(3<<29)
 #define  PIPE_CLK_SEL_DDID		(4<<29)
 #define  PIPE_CLK_SEL_DDIE		(5<<29)
+
+/* Global time clock */
+#define GTCCLK_EN				0xC6030
+#define  GTCCLK_EN_ENABLE		(1<<0)
+
 #endif /* _I915_REG_H_ */
-- 
1.7.9.2

[PATCH 19/37] drm/i915: add LCPLL control registers

[Eugeni Dodonov]

Those are used to control the display core clock.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |    7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 03fb10d..fa9e3a8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4014,4 +4014,11 @@
 #define GTCCLK_EN				0xC6030
 #define  GTCCLK_EN_ENABLE		(1<<0)
 
+/* LCPLL Control */
+#define LCPLL_CTL				0x130040
+#define  LCPLL_PLL_ENABLE		(1<<31)
+#define  LCPLL_PLL_LOCK			(1<<30)
+#define  LCPLL_CD_CLOCK_DISABLE	(1<<25)
+#define  LCPLL_CD2X_CLOCK_DISABLE	(1<<23)
+
 #endif /* _I915_REG_H_ */
-- 
1.7.9.2

[PATCH 20/37] drm/i915: add WM_LINETIME registers

[Eugeni Dodonov]

Watermark line time registers for display low power watermark.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |   10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fa9e3a8..76f7acb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4021,4 +4021,14 @@
 #define  LCPLL_CD_CLOCK_DISABLE	(1<<25)
 #define  LCPLL_CD2X_CLOCK_DISABLE	(1<<23)
 
+/* Pipe WM_LINETIME - watermark line time */
+#define PIPE_WM_LINETIME_A		0x45270
+#define PIPE_WM_LINETIME_B		0x45274
+#define PIPE_WM_LINETIME(pipe) _PIPE(pipe, \
+					PIPE_WM_LINETIME_A, \
+					PIPE_WM_LINETIME_A)
+#define   PIPE_WM_LINETIME_LINETIME_MASK		(0x1ff)
+#define   PIPE_WM_LINETIME_LINETIME(x)			((x))
+#define   PIPE_WM_LINETIME_IPS_LINETIME_MASK	(0x1ff<<16)
+#define   PIPE_WM_LINETIME_IPS_LINETIME(x)		((x)<<16)
 #endif /* _I915_REG_H_ */
-- 
1.7.9.2

[PATCH 21/37] drm/i915: calculate watermarks on Gen7 archs in one place

[Eugeni Dodonov]

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c225de4..46633fe 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4649,7 +4649,7 @@ void sandybridge_update_wm(struct drm_device *dev)
 	}
 
 	/* IVB has 3 pipes */
-	if (IS_IVYBRIDGE(dev) &&
+	if (IS_GEN7(dev) &&
 	    g4x_compute_wm0(dev, 2,
 			    &sandybridge_display_wm_info, latency,
 			    &sandybridge_cursor_wm_info, latency,
-- 
1.7.9.2

[PATCH 22/37] drm/i915: program WM_LINETIME on Haswell

[Eugeni Dodonov]

The line time can be programmed according to the number of horizontal
pixels vs effective pixel rate ratio.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 46633fe..e056c32 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6073,6 +6073,17 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 		   (adjusted_mode->crtc_vsync_start - 1) |
 		   ((adjusted_mode->crtc_vsync_end - 1) << 16));
 
+	if (IS_HASWELL(dev)) {
+		temp = I915_READ(PIPE_WM_LINETIME(pipe));
+		temp &= ~PIPE_WM_LINETIME_LINETIME_MASK;
+
+		/* Pipe horizontal total number of pixels / pixel rate in MHz. */
+		temp |= PIPE_WM_LINETIME_LINETIME(
+				adjusted_mode->crtc_hdisplay /
+				(adjusted_mode->clock / 1000));
+		I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
+	}
+
 	/* pipesrc controls the size that is scaled from, which should
 	 * always be the user's requested size.
 	 */
-- 
1.7.9.2

[PATCH 23/37] drm/i915: do not set 6BPP dithering on haswell

[Eugeni Dodonov]

We don't have those bits on Haswell anymore, so do not set them.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e056c32..24a0a6c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5335,9 +5335,10 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 	pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
 	if (is_dp) {
 		if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
-			pipeconf |= PIPECONF_BPP_6 |
-				    PIPECONF_DITHER_EN |
+			pipeconf |= PIPECONF_DITHER_EN |
 				    PIPECONF_DITHER_TYPE_SP;
+			if (!IS_HASWELL(dev))
+				pipeconf |= PIPECONF_BPP_6;
 		}
 	}
 
-- 
1.7.9.2

[PATCH 24/37] drm/i915: share forcewaking code between IVB and HSW

[Eugeni Dodonov]

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 24a0a6c..27ab70d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8906,7 +8906,7 @@ static void intel_init_display(struct drm_device *dev)
 		dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
 
 		/* IVB configs may use multi-threaded forcewake */
-		if (IS_IVYBRIDGE(dev)) {
+		if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
 			u32	ecobus;
 
 			/* A small trick here - if the bios hasn't configured MT forcewake,
-- 
1.7.9.2

[PATCH 25/37] drm/i915: haswell has 3 pipes as well

[Eugeni Dodonov]

They work differently, but the count is the same.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 9341eb8..a2c0e75 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -2073,7 +2073,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
 	spin_lock_init(&dev_priv->error_lock);
 	spin_lock_init(&dev_priv->rps_lock);
 
-	if (IS_IVYBRIDGE(dev))
+	if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
 		dev_priv->num_pipe = 3;
 	else if (IS_MOBILE(dev) || !IS_GEN2(dev))
 		dev_priv->num_pipe = 2;
-- 
1.7.9.2

[PATCH 26/37] drm/i915: reuse Ivybridge interrupts code for Haswell

[Eugeni Dodonov]

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index afd4e03..ede51f0 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1810,7 +1810,7 @@ static void ironlake_irq_preinstall(struct drm_device *dev)
 
 	INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
 	INIT_WORK(&dev_priv->error_work, i915_error_work_func);
-	if (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
+	if (IS_GEN6(dev) || IS_GEN7(dev))
 		INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
 
 	I915_WRITE(HWSTAM, 0xeffe);
@@ -2136,7 +2136,7 @@ void intel_irq_init(struct drm_device *dev)
 {
 	dev->driver->get_vblank_counter = i915_get_vblank_counter;
 	dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
-	if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
+	if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_GEN7(dev)) {
 		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
 		dev->driver->get_vblank_counter = gm45_get_vblank_counter;
 	}
@@ -2147,7 +2147,7 @@ void intel_irq_init(struct drm_device *dev)
 		dev->driver->get_vblank_timestamp = NULL;
 	dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
 
-	if (IS_IVYBRIDGE(dev)) {
+	if (IS_GEN7(dev)) {
 		/* Share pre & uninstall handlers with ILK/SNB */
 		dev->driver->irq_handler = ivybridge_irq_handler;
 		dev->driver->irq_preinstall = ironlake_irq_preinstall;
-- 
1.7.9.2

[PATCH 27/37] drm/i915: share pipe count handling with Ivybridge

[Eugeni Dodonov]

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 27ab70d..2978597 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2308,7 +2308,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
 	case 1:
 		break;
 	case 2:
-		if (IS_IVYBRIDGE(dev))
+		if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
 			break;
 		/* fall through otherwise */
 	default:
-- 
1.7.9.2

[PATCH 28/37] drm/i915: share IVB cursor routine with Haswell

[Eugeni Dodonov]

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2978597..3b3dc15 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6467,7 +6467,7 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
 	if (!visible && !intel_crtc->cursor_visible)
 		return;
 
-	if (IS_IVYBRIDGE(dev)) {
+	if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
 		I915_WRITE(CURPOS_IVB(pipe), pos);
 		ivb_update_cursor(crtc, base);
 	} else {
-- 
1.7.9.2

[PATCH 29/37] drm/i915: enable power wells on haswell init

[Eugeni Dodonov]

This attempts to enable all the available power wells during the
initialization.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3b3dc15..2c5b953 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9142,6 +9142,34 @@ static void i915_disable_vga(struct drm_device *dev)
 	POSTING_READ(vga_reg);
 }
 
+/* Starting with Haswell, we have different power wells for
+ * different parts of the GPU. This attempts to enable them all.
+ */
+static void intel_init_power_wells(struct drm_device *dev)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	unsigned long power_wells[] = {
+		HSW_PWR_WELL_CTL1,
+		HSW_PWR_WELL_CTL2,
+		HSW_PWR_WELL_CTL4
+	};
+	int i;
+
+	mutex_lock(&dev->struct_mutex);
+
+	for (i = 0; i < ARRAY_SIZE(power_wells); i++) {
+		int well = I915_READ(power_wells[i]);
+
+		if ((well & HSW_PWR_WELL_STATE) == 0) {
+			I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
+			if (wait_for(I915_READ(power_wells[i] & HSW_PWR_WELL_STATE), 20))
+				DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);
+		}
+	}
+
+	mutex_unlock(&dev->struct_mutex);
+}
+
 void intel_modeset_init(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -9159,6 +9187,9 @@ void intel_modeset_init(struct drm_device *dev)
 
 	intel_init_quirks(dev);
 
+	if (IS_HASWELL(dev))
+		intel_init_power_wells(dev);
+
 	intel_init_display(dev);
 
 	if (IS_GEN2(dev)) {
-- 
1.7.9.2

[PATCH 30/37] drm/i915: disable rc6 on haswell for now

[Eugeni Dodonov]

This needs proper enablement to avoid machine hangs, so let's just avoid
it for now.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2c5b953..f7dbcab 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8275,6 +8275,10 @@ static bool intel_enable_rc6(struct drm_device *dev)
 	if (INTEL_INFO(dev)->gen == 5)
 		return 0;
 
+	/* Sorry Haswell, no RC6 for you for now. */
+	if (IS_HASWELL(dev))
+		return 0;
+
 	/*
 	 * Disable rc6 on Sandybridge
 	 */
-- 
1.7.9.2

[PATCH 31/37] drm/i915: enable PCH earlier

[Eugeni Dodonov]

The modesetting sequence for PCH-related connections mentions that the
order of plane/pipe enablement could happen either before of after PCH
enablement.

With LPT, however, we need to enable some things earlier to be able to
talk to PCH. So let's do it a bit in advance.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f7dbcab..b1ad10a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3140,12 +3140,12 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
 	 */
 	intel_crtc_load_lut(crtc);
 
-	intel_enable_pipe(dev_priv, pipe, is_pch_port);
-	intel_enable_plane(dev_priv, plane, pipe);
-
 	if (is_pch_port)
 		ironlake_pch_enable(crtc);
 
+	intel_enable_pipe(dev_priv, pipe, is_pch_port);
+	intel_enable_plane(dev_priv, plane, pipe);
+
 	mutex_lock(&dev->struct_mutex);
 	intel_update_fbc(dev);
 	mutex_unlock(&dev->struct_mutex);
-- 
1.7.9.2

[PATCH 32/37] drm/i915: perform Haswell DDI link training in FDI mode

[Eugeni Dodonov]

This patch attempts at following the modeset sequence closely, retrying
with different voltages if the DP_TP_STATUS reports a failed training.

For training, we add a table of recommended settings for FDI, HDMI and DP
connections. For FDI and DP modes, we also add the HDMI buffer
translation as the last item. Those are ignored in such modes, so there is
no harm in having them set.

Initially, we use DDI E for FDI connectivity.  This is the suggested
configuration, and this seems to be what should work the best with FDI.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |  170 ++++++++++++++++++++++++++++++++++
 1 file changed, 170 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b1ad10a..04625d5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1409,6 +1409,16 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
 		/* FIXME: assert CPU port conditions for SNB+ */
 	}
 
+	/* On HSW, enable PIPE_DDI_FUNC_CTL for the pipe */
+	if (IS_HASWELL(dev_priv->dev)) {
+		I915_WRITE(DDI_FUNC_CTL(pipe),
+				I915_READ(DDI_FUNC_CTL(pipe)) |
+					PIPE_DDI_SELECT_DDI_E |
+					PIPE_DDI_PORT_WIDTH_X2 |
+					PIPE_DDI_MODE_SELECT_FDI |
+					PIPE_DDI_FUNC_ENABLE);
+	}
+
 	reg = PIPECONF(pipe);
 	val = I915_READ(reg);
 	if (val & PIPECONF_ENABLE)
@@ -2698,6 +2708,151 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
 	DRM_DEBUG_KMS("FDI train done.\n");
 }
 
+static const long hsw_ddi_translations_dp[] = {
+	0x00FFFFFF, 0x0006000E,
+	0x00D75FFF, 0x0005000A,
+	0x00C30FFF, 0x00040006,
+	0x80AAAFFF, 0x000B0000,
+	0x00FFFFFF, 0x0005000A,
+	0x00D75FFF, 0x000C0004,
+	0x80C30FFF, 0x000B0000,
+	0x00FFFFFF, 0x00040006,
+	0x80D75FFF, 0x000B0000,
+	0x00FFFFFF, 0x00040006
+};
+
+static const long hsw_ddi_translations_fdi[] = {
+	0x00FFFFFF, 0x0007000E,
+	0x00D75FFF, 0x000F000A,
+	0x00C30FFF, 0x00060006,
+	0x00AAAFFF, 0x001E0000,
+	0x00FFFFFF, 0x000F000A,
+	0x00D75FFF, 0x00160004,
+	0x00C30FFF, 0x001E0000,
+	0x00FFFFFF, 0x00060006,
+	0x00D75FFF, 0x001E0000,
+	0x00FFFFFF, 0x00040006
+};
+
+/* For HDMI, we are only interested in the last entry */
+static const long hsw_ddi_translations_hdmi[] = {
+	0x0, 0x0,
+	0x0, 0x0,
+	0x0, 0x0,
+	0x0, 0x0,
+	0x0, 0x0,
+	0x0, 0x0,
+	0x0, 0x0,
+	0x0, 0x0,
+	0x0, 0x0,
+	0x00FFFFFF, 0x00040006
+};
+
+
+static const long hsw_ddi_buf_ctl_values[] = {
+	DDI_BUF_EMP_400MV_0DB_HSW,
+	DDI_BUF_EMP_400MV_3_5DB_HSW,
+	DDI_BUF_EMP_400MV_6DB_HSW,
+	DDI_BUF_EMP_400MV_9_5DB_HSW,
+	DDI_BUF_EMP_600MV_0DB_HSW,
+	DDI_BUF_EMP_600MV_3_5DB_HSW,
+	DDI_BUF_EMP_600MV_6DB_HSW,
+	DDI_BUF_EMP_800MV_0DB_HSW,
+	DDI_BUF_EMP_800MV_3_5DB_HSW
+};
+
+
+/* Link training for HSW parts */
+static void hsw_fdi_link_train(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int pipe = intel_crtc->pipe;
+	u32 reg, temp, i;
+
+	/* Prior to enabling DDI, configure buffer translation with FDI values */
+	for (i=0, reg=DDI_BUF_TRANS_E; i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
+		I915_WRITE(reg, hsw_ddi_translations_fdi[i]);
+		reg += 4;
+	}
+
+	/* Configure CPU PLL, wait for warmup */
+	I915_WRITE(SPLL_CTL,
+			SPLL_PLL_ENABLE |
+			SPLL_PLL_FREQ_1350MHz |
+			SPLL_PLL_SCC);
+
+	/* Use SPLL to drive the output when in FDI mode */
+	I915_WRITE(PORT_CLK_SEL_E,
+			PORT_CLK_SEL_SPLL);
+	I915_WRITE(PIPE_CLK_SEL(pipe),
+			PIPE_CLK_SEL_DDIE);
+
+	udelay(20);
+
+	/* Start the training iterating through available voltages and emphasis */
+	for (i=0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values); i++) {
+		/* Configure DP_TP_CTL with auto-training */
+		I915_WRITE(DP_TP_CTL_E,
+					DP_TP_CTL_FDI_AUTOTRAIN |
+					DP_TP_CTL_ENHANCED_FRAME_ENABLE |
+					DP_TP_CTL_LINK_TRAIN_PAT1 |
+					DP_TP_CTL_ENABLE);
+
+		/* Configure and enable DDI_BUF_CTL for DDI E with next voltage */
+		temp = I915_READ(DDI_BUF_CTL_E);
+		temp = (temp & ~DDI_BUF_EMP_MASK);
+		I915_WRITE(DDI_BUF_CTL_E,
+				temp |
+				DDI_BUF_CTL_ENABLE |
+				DDI_PORT_WIDTH_X2 |
+				hsw_ddi_buf_ctl_values[i]);
+
+		udelay(600);
+
+		/* Enable CPU FDI Receiver with auto-training */
+		I915_WRITE(FDI_RX_CTL(pipe),
+				I915_READ(FDI_RX_CTL(pipe)) |
+					FDI_LINK_TRAIN_AUTO |
+					FDI_RX_ENABLE |
+					FDI_LINK_TRAIN_PATTERN_1_CPT |
+					FDI_RX_ENHANCE_FRAME_ENABLE |
+					LPT_FDI_PORT_WIDTH_2X |
+					FDI_RX_PLL_ENABLE);
+		POSTING_READ(reg);
+		udelay(100);
+
+		temp = I915_READ(DP_TP_STATUS_E);
+		if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
+			DRM_INFO("BUF_CTL training done on %d step\n", i);
+
+			/* Enable normal pixel sending for FDI */
+			I915_WRITE(DP_TP_CTL_E,
+						DP_TP_CTL_FDI_AUTOTRAIN |
+						DP_TP_CTL_LINK_TRAIN_NORMAL |
+						DP_TP_CTL_ENHANCED_FRAME_ENABLE |
+						DP_TP_CTL_ENABLE);
+
+			break;
+		} else {
+			DRM_ERROR("Error training BUF_CTL %d\n", i);
+
+			/* Disable DP_TP_CTL and FDI_RX_CTL) and retry */
+			I915_WRITE(DP_TP_CTL_E,
+					I915_READ(DP_TP_CTL_E) &
+						~DP_TP_CTL_ENABLE);
+			I915_WRITE(FDI_RX_CTL(pipe),
+					I915_READ(FDI_RX_CTL(pipe)) &
+						~FDI_RX_PLL_ENABLE);
+			continue;
+		}
+	}
+
+
+	DRM_DEBUG_KMS("FDI train done.\n");
+}
+
 /* Manual link training for Ivy Bridge A0 parts */
 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
 {
@@ -3019,6 +3174,10 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 			temp |= (TRANSC_DPLL_ENABLE | transc_sel);
 		}
 		I915_WRITE(PCH_DPLL_SEL, temp);
+	} else if (HAS_PCH_LPT(dev)) {
+		/* DDIE clock is recommented for FDI connections */
+		I915_WRITE(PIPE_CLK_SEL(pipe),
+				PIPE_CLK_SEL_DDIE);
 	}
 
 	/* set transcoder timing, panel must allow it */
@@ -8975,6 +9134,17 @@ static void intel_init_display(struct drm_device *dev)
 			}
 			dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
 			dev_priv->display.write_eld = ironlake_write_eld;
+		} else if (IS_HASWELL(dev)) {
+			dev_priv->display.fdi_link_train = hsw_fdi_link_train;
+			if (SNB_READ_WM0_LATENCY()) {
+				dev_priv->display.update_wm = sandybridge_update_wm;
+			} else {
+				DRM_DEBUG_KMS("Failed to read display plane latency. "
+					      "Disable CxSR\n");
+				dev_priv->display.update_wm = NULL;
+			}
+			dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
+			dev_priv->display.write_eld = ironlake_write_eld;
 		} else
 			dev_priv->display.update_wm = NULL;
 	} else if (IS_PINEVIEW(dev)) {
-- 
1.7.9.2

[PATCH 33/37] drm/i915: double-write DDI translation table

[Eugeni Dodonov]

Some double-buffered registers need to be written twice.

Note that it is being sent as a separate patch because sometimes these
registers do work when written only once. But double-writing on my machine
ensured that they work more often.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 04625d5..8a839be 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2769,12 +2769,16 @@ static void hsw_fdi_link_train(struct drm_crtc *crtc)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 	int pipe = intel_crtc->pipe;
-	u32 reg, temp, i;
+	u32 reg, temp, i, j;
 
 	/* Prior to enabling DDI, configure buffer translation with FDI values */
-	for (i=0, reg=DDI_BUF_TRANS_E; i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
-		I915_WRITE(reg, hsw_ddi_translations_fdi[i]);
-		reg += 4;
+	/* Those registers seem to be double-buffered - at least, the hw team writes them twice. */
+	for (j=0; j < 2; j++) {
+		for (i=0, reg=DDI_BUF_TRANS_E; i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
+			I915_WRITE(reg, hsw_ddi_translations_fdi[i]);
+			reg += 4;
+		}
+		udelay(20);
 	}
 
 	/* Configure CPU PLL, wait for warmup */
-- 
1.7.9.2

[PATCH 34/37] drm/i915: do not use fdi_normal_train on haswell

[Eugeni Dodonov]

This should be already configured when FDI auto-negotiation is done.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8a839be..5f6cb35 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3195,7 +3195,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 	I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
 	I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
 
-	intel_fdi_normal_train(crtc);
+	if (!IS_HASWELL(dev))
+		intel_fdi_normal_train(crtc);
 
 	/* For PCH DP, enable TRANS_DP_CTL */
 	if (HAS_PCH_CPT(dev) &&
-- 
1.7.9.2

[PATCH 35/37] drm/i915: program iCLKIP on Lynx Point

[Eugeni Dodonov]

The iCLKIP clock is used to drive the VGA pixel clock on the PCH. In order
to do so, it must be programmed to properly do the clock ticks according
to the divisor, phase direction, phase increments and a special auxiliary
divisor for 20MHz clock.

Those values can be programmed individually, by doing some math; or we
could use a pre-defined table of values for each modeset. For speed and
simplification, the idea was to just adopt the table of valid pixel clocks
and select the matching iCLKIP values from there.

As a possible idea for the future, it would be possible to add a fallback
and calculate those values manually in case no match is found. But I don't
think we'll encounter a mode not covered by those table, and VGA is pretty
much going away in the future anyway.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |  309 ++++++++++++++++++++++++++++++++++
 1 file changed, 309 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5f6cb35..a37e0b7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2761,6 +2761,312 @@ static const long hsw_ddi_buf_ctl_values[] = {
 	DDI_BUF_EMP_800MV_3_5DB_HSW
 };
 
+/* Available pixel clock values */
+struct iclk_vga_clock {
+	u32 clock;
+	u16 auxdiv;
+	u16 divsel;
+	u16 phasedir;
+	u16 phaseinc;
+};
+
+static const struct iclk_vga_clock iclk_vga_clock_table[] = {
+	{20000,	1,	0x41,	0,	0x20},	/* 20000 ppm=0 */
+	{21000,	0,	0x7E,	0,	0x25},	/* 20999 ppm=-53 */
+	{21912,	0,	0x79,	0,	0x0E},	/* 21912 ppm=12 */
+	{22000,	0,	0x78,	0,	0x2F},	/* 21999 ppm=-58 */
+	{23000,	0,	0x73,	0,	0x19},	/* 23000 ppm=6 */
+	{24000,	0,	0x6E,	0,	0x20},	/* 24000 ppm=0 */
+	{25000,	0,	0x6A,	0,	0x00},	/* 25000 ppm=0 */
+	{25175,	0,	0x69,	0,	0x10},	/* 25175 ppm=-7 */
+	{25200,	0,	0x69,	0,	0x09},	/* 25201 ppm=21 */
+	{26000,	0,	0x66,	1,	0x0A},	/* 26001 ppm=24 */
+	{27000,	0,	0x62,	0,	0x00},	/* 27000 ppm=0 */
+	{27027,	0,	0x62,	1,	0x06},	/* 27025 ppm=-62 */
+	{27500,	0,	0x60,	0,	0x0C},	/* 27498 ppm=-58 */
+	{28000,	0,	0x5E,	0,	0x1B},	/* 28002 ppm=70 */
+	{28320,	0,	0x5D,	0,	0x16},	/* 28319 ppm=-50 */
+	{28322,	0,	0x5D,	0,	0x15},	/* 28323 ppm=44 */
+	{29000,	0,	0x5B,	0,	0x07},	/* 28998 ppm=-64 */
+	{30000,	0,	0x58,	0,	0x00},	/* 30000 ppm=0 */
+	{31000,	0,	0x55,	0,	0x06},	/* 31001 ppm=35 */
+	{31500,	0,	0x54,	1,	0x12},	/* 31498 ppm=-53 */
+	{32000,	0,	0x52,	0,	0x18},	/* 32000 ppm=0 */
+	{32500,	0,	0x51,	0,	0x05},	/* 32500 ppm=-15 */
+	{33000,	0,	0x50,	1,	0x0C},	/* 33002 ppm=70 */
+	{34000,	0,	0x4D,	0,	0x1A},	/* 34002 ppm=70 */
+	{35000,	0,	0x4B,	0,	0x09},	/* 35001 ppm=29 */
+	{35500,	0,	0x4A,	0,	0x04},	/* 35497 ppm=-82 */
+	{36000,	0,	0x49,	0,	0x00},	/* 36000 ppm=0 */
+	{37000,	0,	0x47,	1,	0x02},	/* 37002 ppm=58 */
+	{38000,	0,	0x45,	0,	0x03},	/* 38003 ppm=82 */
+	{39000,	0,	0x43,	0,	0x0F},	/* 38998 ppm=-53 */
+	{40000,	0,	0x41,	0,	0x20},	/* 40000 ppm=0 */
+	{40500,	0,	0x41,	1,	0x15},	/* 40497 ppm=-79 */
+	{40541,	0,	0x41,	1,	0x1A},	/* 40544 ppm=95 */
+	{41000,	0,	0x40,	1,	0x09},	/* 40996 ppm=-87 */
+	{41540,	0,	0x3F,	0,	0x00},	/* 41538 ppm=-38 */
+	{42000,	0,	0x3E,	0,	0x12},	/* 42003 ppm=70 */
+	{43000,	0,	0x3D,	1,	0x0D},	/* 42996 ppm=-99 */
+	{43163,	0,	0x3D,	1,	0x1D},	/* 43168 ppm=108 */
+	{44000,	0,	0x3B,	0,	0x17},	/* 44003 ppm=70 */
+	{44900,	0,	0x3A,	0,	0x09},	/* 44895 ppm=-117 */
+	{45000,	0,	0x3A,	0,	0x00},	/* 45000 ppm=0 */
+	{46000,	0,	0x39,	1,	0x13},	/* 45994 ppm=-128 */
+	{47000,	0,	0x37,	0,	0x1D},	/* 46995 ppm=-110 */
+	{48000,	0,	0x36,	0,	0x10},	/* 48000 ppm=0 */
+	{49000,	0,	0x35,	0,	0x07},	/* 48993 ppm=-134 */
+	{49500,	0,	0x35,	1,	0x1D},	/* 49499 ppm=-27 */
+	{50000,	0,	0x34,	0,	0x00},	/* 50000 ppm=0 */
+	{51000,	0,	0x33,	1,	0x04},	/* 51004 ppm=70 */
+	{52000,	0,	0x32,	1,	0x05},	/* 52001 ppm=24 */
+	{52406,	0,	0x32,	1,	0x1F},	/* 52411 ppm=101 */
+	{53000,	0,	0x31,	1,	0x04},	/* 53006 ppm=116 */
+	{54000,	0,	0x30,	0,	0x00},	/* 54000 ppm=0 */
+	{54054,	0,	0x30,	1,	0x03},	/* 54051 ppm=-62 */
+	{55000,	0,	0x2F,	0,	0x06},	/* 54997 ppm=-58 */
+	{56000,	0,	0x2E,	0,	0x0E},	/* 55995 ppm=-93 */
+	{56250,	0,	0x2E,	0,	0x00},	/* 56250 ppm=0 */
+	{57000,	0,	0x2D,	0,	0x18},	/* 56992 ppm=-139 */
+	{58000,	0,	0x2D,	1,	0x1D},	/* 58006 ppm=105 */
+	{59000,	0,	0x2C,	1,	0x0F},	/* 58996 ppm=-64 */
+	{60000,	0,	0x2B,	0,	0x00},	/* 60000 ppm=0 */
+	{61000,	0,	0x2A,	0,	0x11},	/* 60995 ppm=-76 */
+	{62000,	0,	0x2A,	1,	0x1D},	/* 62002 ppm=35 */
+	{63000,	0,	0x29,	1,	0x09},	/* 62997 ppm=-53 */
+	{64000,	0,	0x28,	0,	0x0C},	/* 64000 ppm=0 */
+	{65000,	0,	0x28,	1,	0x1E},	/* 65011 ppm=174 */
+	{66000,	0,	0x27,	1,	0x06},	/* 66005 ppm=70 */
+	{66667,	0,	0x26,	0,	0x20},	/* 66667 ppm=-5 */
+	{67000,	0,	0x26,	0,	0x13},	/* 67003 ppm=41 */
+	{68000,	0,	0x26,	1,	0x13},	/* 68005 ppm=70 */
+	{68179,	0,	0x26,	1,	0x19},	/* 68166 ppm=-196 */
+	{69000,	0,	0x25,	0,	0x08},	/* 69010 ppm=139 */
+	{70000,	0,	0x25,	1,	0x1B},	/* 69988 ppm=-174 */
+	{71000,	0,	0x24,	0,	0x02},	/* 70994 ppm=-82 */
+	{72000,	0,	0x23,	0,	0x20},	/* 72000 ppm=0 */
+	{73000,	0,	0x23,	1,	0x01},	/* 73004 ppm=53 */
+	{74000,	0,	0x22,	0,	0x1F},	/* 74004 ppm=58 */
+	{74175,	0,	0x22,	0,	0x1A},	/* 74163 ppm=-161 */
+	{74250,	0,	0x22,	0,	0x17},	/* 74259 ppm=118 */
+	{74481,	0,	0x22,	0,	0x10},	/* 74483 ppm=24 */
+	{75000,	0,	0x22,	0,	0x00},	/* 75000 ppm=0 */
+	{76000,	0,	0x22,	1,	0x1E},	/* 75989 ppm=-139 */
+	{77000,	0,	0x21,	0,	0x04},	/* 77005 ppm=70 */
+	{78000,	0,	0x21,	1,	0x19},	/* 78014 ppm=174 */
+	{78750,	0,	0x20,	0,	0x12},	/* 78760 ppm=131 */
+	{79000,	0,	0x20,	0,	0x0B},	/* 79012 ppm=157 */
+	{80000,	0,	0x20,	1,	0x10},	/* 80000 ppm=0 */
+	{81000,	0,	0x1F,	0,	0x15},	/* 81013 ppm=157 */
+	{81081,	0,	0x1F,	0,	0x13},	/* 81089 ppm=95 */
+	{81624,	0,	0x1F,	0,	0x05},	/* 81625 ppm=12 */
+	{82000,	0,	0x1F,	1,	0x05},	/* 82012 ppm=151 */
+	{83000,	0,	0x1F,	1,	0x1E},	/* 82997 ppm=-35 */
+	{83950,	0,	0x1E,	0,	0x0A},	/* 83965 ppm=179 */
+	{84000,	0,	0x1E,	0,	0x09},	/* 84006 ppm=70 */
+	{85000,	0,	0x1E,	1,	0x0F},	/* 84998 ppm=-29 */
+	{86000,	0,	0x1D,	0,	0x19},	/* 86013 ppm=151 */
+	{87000,	0,	0x1D,	0,	0x02},	/* 87009 ppm=105 */
+	{88000,	0,	0x1D,	1,	0x14},	/* 87984 ppm=-186 */
+	{89000,	0,	0x1C,	0,	0x16},	/* 88980 ppm=-220 */
+	{90000,	0,	0x1C,	0,	0x00},	/* 90000 ppm=0 */
+	{91000,	0,	0x1C,	1,	0x15},	/* 90995 ppm=-53 */
+	{92000,	0,	0x1B,	0,	0x16},	/* 92013 ppm=139 */
+	{93000,	0,	0x1B,	0,	0x02},	/* 93003 ppm=35 */
+	{94000,	0,	0x1B,	1,	0x12},	/* 94015 ppm=163 */
+	{94500,	0,	0x1B,	1,	0x1B},	/* 94478 ppm=-235 */
+	{95000,	0,	0x1A,	0,	0x1B},	/* 94997 ppm=-29 */
+	{95654,	0,	0x1A,	0,	0x0F},	/* 95628 ppm=-271 */
+	{96000,	0,	0x1A,	0,	0x08},	/* 96000 ppm=0 */
+	{97000,	0,	0x1A,	1,	0x0B},	/* 97024 ppm=249 */
+	{98000,	0,	0x1A,	1,	0x1D},	/* 98015 ppm=151 */
+	{99000,	0,	0x19,	0,	0x11},	/* 99026 ppm=261 */
+	{100000,	0,	0x19,	0,	0x00},	/* 100000 ppm=0 */
+	{101000,	0,	0x19,	1,	0x11},	/* 100994 ppm=-64 */
+	{102000,	0,	0x18,	0,	0x1E},	/* 102007 ppm=70 */
+	{103000,	0,	0x18,	0,	0x0E},	/* 102980 ppm=-197 */
+	{104000,	0,	0x18,	1,	0x02},	/* 103971 ppm=-278 */
+	{105000,	0,	0x18,	1,	0x12},	/* 104982 ppm=-174 */
+	{106000,	0,	0x17,	0,	0x1E},	/* 106012 ppm=116 */
+	{107000,	0,	0x17,	0,	0x0F},	/* 106997 ppm=-29 */
+	{107214,	0,	0x17,	0,	0x0C},	/* 107196 ppm=-168 */
+	{108000,	0,	0x17,	0,	0x00},	/* 108000 ppm=0 */
+	{109000,	0,	0x17,	1,	0x0F},	/* 109022 ppm=203 */
+	{110000,	0,	0x17,	1,	0x1D},	/* 109994 ppm=-58 */
+	{110013,	0,	0x17,	1,	0x1D},	/* 109994 ppm=-177 */
+	{111000,	0,	0x16,	0,	0x15},	/* 110983 ppm=-157 */
+	{111263,	0,	0x16,	0,	0x11},	/* 111269 ppm=55 */
+	{111375,	0,	0x16,	0,	0x10},	/* 111340 ppm=-313 */
+	{112000,	0,	0x16,	0,	0x07},	/* 111990 ppm=-93 */
+	{113000,	0,	0x16,	1,	0x07},	/* 113015 ppm=134 */
+	{113309,	0,	0x16,	1,	0x0B},	/* 113311 ppm=22 */
+	{113100,	0,	0x16,	1,	0x08},	/* 113089 ppm=-98 */
+	{114000,	0,	0x16,	1,	0x14},	/* 113984 ppm=-139 */
+	{115000,	0,	0x15,	0,	0x1F},	/* 114970 ppm=-261 */
+	{116000,	0,	0x15,	0,	0x12},	/* 115973 ppm=-232 */
+	{117000,	0,	0x15,	0,	0x05},	/* 116994 ppm=-53 */
+	{118000,	0,	0x15,	1,	0x08},	/* 118033 ppm=278 */
+	{119000,	0,	0x15,	1,	0x14},	/* 119008 ppm=70 */
+	{119651,	0,	0x15,	1,	0x1C},	/* 119668 ppm=139 */
+	{120000,	0,	0x14,	0,	0x20},	/* 120000 ppm=0 */
+	{121000,	0,	0x14,	0,	0x14},	/* 121008 ppm=70 */
+	{122000,	0,	0x14,	0,	0x08},	/* 122034 ppm=278 */
+	{122614,	0,	0x14,	0,	0x01},	/* 122640 ppm=214 */
+	{123000,	0,	0x14,	1,	0x03},	/* 122989 ppm=-87 */
+	{123379,	0,	0x14,	1,	0x07},	/* 123340 ppm=-313 */
+	{124000,	0,	0x14,	1,	0x0E},	/* 123960 ppm=-324 */
+	{125000,	0,	0x14,	1,	0x1A},	/* 125036 ppm=290 */
+	{126000,	0,	0x13,	0,	0x1B},	/* 126039 ppm=313 */
+	{127000,	0,	0x13,	0,	0x11},	/* 126965 ppm=-272 */
+	{128000,	0,	0x13,	0,	0x06},	/* 128000 ppm=0 */
+	{129000,	0,	0x13,	1,	0x04},	/* 128955 ppm=-348 */
+	{129859,	0,	0x13,	1,	0x0D},	/* 129827 ppm=-245 */
+	{130000,	0,	0x13,	1,	0x0F},	/* 130023 ppm=174 */
+	{131000,	0,	0x13,	1,	0x19},	/* 131008 ppm=64 */
+	{131850,	0,	0x12,	0,	0x1F},	/* 131808 ppm=-321 */
+	{132000,	0,	0x12,	0,	0x1D},	/* 132009 ppm=70 */
+	{133000,	0,	0x12,	0,	0x13},	/* 133025 ppm=192 */
+	{133330,	0,	0x12,	0,	0x10},	/* 133333 ppm=26 */
+	{134000,	0,	0x12,	0,	0x0A},	/* 133953 ppm=-348 */
+	{135000,	0,	0x12,	0,	0x00},	/* 135000 ppm=0 */
+	{136000,	0,	0x12,	1,	0x09},	/* 135956 ppm=-324 */
+	{137000,	0,	0x12,	1,	0x13},	/* 137034 ppm=249 */
+	{138000,	0,	0x12,	1,	0x1C},	/* 138019 ppm=139 */
+	{139000,	0,	0x11,	0,	0x1B},	/* 139019 ppm=134 */
+	{139050,	0,	0x11,	0,	0x1B},	/* 139019 ppm=-227 */
+	{139054,	0,	0x11,	0,	0x1B},	/* 139019 ppm=-256 */
+	{140000,	0,	0x11,	0,	0x12},	/* 140032 ppm=232 */
+	{141000,	0,	0x11,	0,	0x0A},	/* 140946 ppm=-382 */
+	{142000,	0,	0x11,	0,	0x01},	/* 141988 ppm=-82 */
+	{143000,	0,	0x11,	1,	0x08},	/* 143046 ppm=325 */
+	{143472,	0,	0x11,	1,	0x0C},	/* 143522 ppm=346 */
+	{144000,	0,	0x11,	1,	0x10},	/* 144000 ppm=0 */
+	{145000,	0,	0x11,	1,	0x18},	/* 144966 ppm=-232 */
+	{146000,	0,	0x10,	0,	0x20},	/* 145946 ppm=-371 */
+	{147000,	0,	0x10,	0,	0x18},	/* 146939 ppm=-417 */
+	{147891,	0,	0x10,	0,	0x10},	/* 147945 ppm=367 */
+	{148000,	0,	0x10,	0,	0x10},	/* 147945 ppm=-371 */
+	{148350,	0,	0x10,	0,	0x0D},	/* 148326 ppm=-161 */
+	{148500,	0,	0x10,	0,	0x0C},	/* 148454 ppm=-313 */
+	{149000,	0,	0x10,	0,	0x08},	/* 148966 ppm=-232 */
+	{150000,	0,	0x10,	0,	0x00},	/* 150000 ppm=0 */
+	{151000,	0,	0x10,	1,	0x08},	/* 151049 ppm=325 */
+	{152000,	0,	0x10,	1,	0x0F},	/* 151979 ppm=-139 */
+	{152280,	0,	0x10,	1,	0x11},	/* 152247 ppm=-219 */
+	{153000,	0,	0x10,	1,	0x17},	/* 153056 ppm=365 */
+	{154000,	0,	0x10,	1,	0x1E},	/* 154011 ppm=70 */
+	{155000,	0,	0x0F,	0,	0x1B},	/* 154978 ppm=-145 */
+	{156000,	0,	0x0F,	0,	0x14},	/* 155957 ppm=-278 */
+	{157000,	0,	0x0F,	0,	0x0D},	/* 156948 ppm=-330 */
+	{157500,	0,	0x0F,	0,	0x09},	/* 157521 ppm=131 */
+	{158000,	0,	0x0F,	0,	0x06},	/* 157952 ppm=-301 */
+	{159000,	0,	0x0F,	1,	0x01},	/* 158970 ppm=-191 */
+	{160000,	0,	0x0F,	1,	0x08},	/* 160000 ppm=0 */
+	{161000,	0,	0x0F,	1,	0x0F},	/* 161044 ppm=273 */
+	{162000,	0,	0x0F,	1,	0x15},	/* 161949 ppm=-313 */
+	{163000,	0,	0x0F,	1,	0x1C},	/* 163019 ppm=116 */
+	{164000,	0,	0x0E,	0,	0x1E},	/* 163947 ppm=-324 */
+	{165000,	0,	0x0E,	0,	0x17},	/* 165043 ppm=261 */
+	{166000,	0,	0x0E,	0,	0x11},	/* 165994 ppm=-35 */
+	{167000,	0,	0x0E,	0,	0x0B},	/* 166957 ppm=-261 */
+	{168000,	0,	0x0E,	0,	0x05},	/* 167930 ppm=-417 */
+	{169000,	0,	0x0E,	1,	0x02},	/* 169080 ppm=475 */
+	{169128,	0,	0x0E,	1,	0x02},	/* 169080 ppm=-283 */
+	{170000,	0,	0x0E,	1,	0x08},	/* 170079 ppm=464 */
+	{171000,	0,	0x0E,	1,	0x0D},	/* 170920 ppm=-469 */
+	{172000,	0,	0x0E,	1,	0x13},	/* 171940 ppm=-348 */
+	{172800,	0,	0x0E,	1,	0x18},	/* 172800 ppm=0 */
+	{173000,	0,	0x0E,	1,	0x19},	/* 172973 ppm=-157 */
+	{174000,	0,	0x0E,	1,	0x1F},	/* 174018 ppm=105 */
+	{174787,	0,	0x0D,	0,	0x1D},	/* 174722 ppm=-373 */
+	{175000,	0,	0x0D,	0,	0x1B},	/* 175076 ppm=435 */
+	{175500,	0,	0x0D,	0,	0x19},	/* 175431 ppm=-391 */
+	{176000,	0,	0x0D,	0,	0x16},	/* 175967 ppm=-186 */
+	{177000,	0,	0x0D,	0,	0x10},	/* 177049 ppm=278 */
+	{178000,	0,	0x0D,	0,	0x0B},	/* 177961 ppm=-220 */
+	{179000,	0,	0x0D,	0,	0x05},	/* 179067 ppm=377 */
+	{180000,	0,	0x0D,	0,	0x00},	/* 180000 ppm=0 */
+};
+
+/* Program iCLKIP clock to the desired frequency */
+static void lpt_program_iclkip(struct drm_crtc *crtc)
+{
+	struct drm_device *dev = crtc->dev;
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	u32 auxdiv=0, divsel=0, phasedir=0, phaseinc=0, valid=0;
+	u32 temp, i;
+
+	/* Ungate pixel clock */
+	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
+
+	/* Disable SSCCTL */
+	SBI_WRITE(dev_priv, SBI_SSCCTL6,
+				SBI_READ(dev_priv, SBI_SSCCTL6) |
+					SBI_SSCCTL_DISABLE);
+
+	/* Calculating clock values for iCLKIP */
+	for (i=0; i < ARRAY_SIZE(iclk_vga_clock_table); i++) {
+		if (crtc->mode.clock == iclk_vga_clock_table[i].clock) {
+			DRM_INFO("Found clock settings for %dKHz refresh rate\n",
+					crtc->mode.clock);
+
+			auxdiv = iclk_vga_clock_table[i].auxdiv;
+			divsel = iclk_vga_clock_table[i].divsel;
+			phasedir = iclk_vga_clock_table[i].phasedir;
+			phaseinc = iclk_vga_clock_table[i].phaseinc;
+
+			valid = 1;
+
+			break;
+		}
+	}
+
+	if (!valid) {
+		DRM_ERROR("Unable to find iCLKIP clock settings for %dKHz refresh rate\n",
+				crtc->mode.clock);
+		return;
+	}
+
+	/* Program SSCDIVINTPHASE6 with values which HW team uses */
+	DRM_DEBUG("Programming SSCDIVINTPHASE for %dKHz: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
+			crtc->mode.clock,
+			auxdiv,
+			divsel,
+			phasedir,
+			phaseinc);
+
+	/* Program SSCDIVINTPHASE6 */
+	temp = SBI_READ(dev_priv, SBI_SSCDIVINTPHASE6);
+	temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
+	temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
+	temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
+	temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
+	temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
+	temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
+
+	SBI_WRITE(dev_priv,
+			SBI_SSCDIVINTPHASE6,
+			temp);
+
+	/* Program SSCAUXDIV */
+	SBI_WRITE(dev_priv,
+			SBI_SSCAUXDIV6,
+				SBI_READ(dev_priv, SBI_SSCAUXDIV6) |
+					SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv));
+
+
+	/* Enable modulator and associated divider */
+	SBI_WRITE(dev_priv, SBI_SSCCTL6,
+				SBI_READ(dev_priv, SBI_SSCCTL6) &
+					~SBI_SSCCTL_DISABLE);
+
+	/* Wait for initialization time */
+	udelay(50);
+
+	/* Gate pixel clock */
+	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
+}
+
 
 /* Link training for HSW parts */
 static void hsw_fdi_link_train(struct drm_crtc *crtc)
@@ -3182,6 +3488,9 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 		/* DDIE clock is recommented for FDI connections */
 		I915_WRITE(PIPE_CLK_SEL(pipe),
 				PIPE_CLK_SEL_DDIE);
+
+		/* Program iCLKIP */
+		lpt_program_iclkip(crtc);
 	}
 
 	/* set transcoder timing, panel must allow it */
-- 
1.7.9.2

[PATCH 36/37] drm/i915: add warning when using old bits on Haswell/LPT

[Eugeni Dodonov]

Those have different functionality on Haswell architecture, so let's
trigger a warning message when we are going through a path we should not
go into on Haswell.

This patch is here for make debugging and log tracing easier, it should
go away in the future, we we'll stop hitting those code paths.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |   59 +++++++++++++++++++++++++++-------
 1 file changed, 47 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a37e0b7..10b92e8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -847,9 +847,16 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 	u32 val;
 	bool cur_state;
 
-	reg = FDI_TX_CTL(pipe);
-	val = I915_READ(reg);
-	cur_state = !!(val & FDI_TX_ENABLE);
+	if (IS_HASWELL(dev_priv->dev)) {
+		DRM_ERROR("Attempting to check FDI_TX_CTL on Haswell, using DDI instead\n");
+		reg = DDI_FUNC_CTL(pipe);
+		val = I915_READ(reg);
+		cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
+	} else {
+		reg = FDI_TX_CTL(pipe);
+		val = I915_READ(reg);
+		cur_state = !!(val & FDI_TX_ENABLE);
+	}
 	WARN(cur_state != state,
 	     "FDI TX state assertion failure (expected %s, current %s)\n",
 	     state_string(state), state_string(cur_state));
@@ -864,9 +871,14 @@ static void assert_fdi_rx(struct drm_i915_private *dev_priv,
 	u32 val;
 	bool cur_state;
 
-	reg = FDI_RX_CTL(pipe);
-	val = I915_READ(reg);
-	cur_state = !!(val & FDI_RX_ENABLE);
+	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
+			DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
+			return;
+	} else {
+		reg = FDI_RX_CTL(pipe);
+		val = I915_READ(reg);
+		cur_state = !!(val & FDI_RX_ENABLE);
+	}
 	WARN(cur_state != state,
 	     "FDI RX state assertion failure (expected %s, current %s)\n",
 	     state_string(state), state_string(cur_state));
@@ -884,6 +896,11 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
 	if (dev_priv->info->gen == 5)
 		return;
 
+	if (IS_HASWELL(dev_priv->dev)) {
+		DRM_ERROR("Attempting to check FDI_TX_PLL on Haswell, aborting\n");
+		return;
+	}
+
 	reg = FDI_TX_CTL(pipe);
 	val = I915_READ(reg);
 	WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
@@ -895,6 +912,10 @@ static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
 	int reg;
 	u32 val;
 
+	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
+		DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
+		return;
+	}
 	reg = FDI_RX_CTL(pipe);
 	val = I915_READ(reg);
 	WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
@@ -1000,6 +1021,11 @@ static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
 	u32 val;
 	bool enabled;
 
+	if (HAS_PCH_LPT(dev_priv->dev)) {
+		DRM_ERROR("LPT does not has PCH refclk, skipping check\n");
+		return;
+	}
+
 	val = I915_READ(PCH_DREF_CONTROL);
 	enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
 			    DREF_SUPERSPREAD_SOURCE_MASK));
@@ -1323,6 +1349,10 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
 	assert_fdi_tx_enabled(dev_priv, pipe);
 	assert_fdi_rx_enabled(dev_priv, pipe);
 
+	if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
+		DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
+		return;
+	}
 	reg = TRANSCONF(pipe);
 	val = I915_READ(reg);
 	pipeconf_val = I915_READ(PIPECONF(pipe));
@@ -3308,13 +3338,18 @@ static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
 	udelay(200);
 
 	/* Enable CPU FDI TX PLL, always on for Ironlake */
-	reg = FDI_TX_CTL(pipe);
-	temp = I915_READ(reg);
-	if ((temp & FDI_TX_PLL_ENABLE) == 0) {
-		I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
+	if (IS_HASWELL(dev)) {
+		DRM_ERROR("Skipping enablement of FDI_TX_PLL on Haswell\n");
+		return;
+	} else {
+		reg = FDI_TX_CTL(pipe);
+		temp = I915_READ(reg);
+		if ((temp & FDI_TX_PLL_ENABLE) == 0) {
+			I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
 
-		POSTING_READ(reg);
-		udelay(100);
+			POSTING_READ(reg);
+			udelay(100);
+		}
 	}
 }
 
-- 
1.7.9.2

[PATCH 37/37] drm/i915: dump registers read/write ops

[Eugeni Dodonov]

This logs all the registers and SBI accesses as they happen.

Note that it is not supposed to go into the final patch series. But there
are too many subtle changes in both HSW and LPT that are much easier to
spot with this extra debugging when attaching a dmesg output in case of
problems.

In other words, this is ugly, but if you run into an issue and send me
dmesg with those included, my chances of investigating the problems will
increase exponentially.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c      |    2 ++
 drivers/gpu/drm/i915/intel_display.c |    2 ++
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5fe9d62..f75d16f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1022,6 +1022,7 @@ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
 		val = read##y(dev_priv->regs + reg); \
 	} \
 	trace_i915_reg_rw(false, reg, val, sizeof(val)); \
+	DRM_DEBUG("I915_READ: 0x%x = 0x%x\n", reg, val); \
 	return val; \
 }
 
@@ -1034,6 +1035,7 @@ __i915_read(64, q)
 #define __i915_write(x, y) \
 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
 	u32 __fifo_ret = 0; \
+	DRM_DEBUG("I915_WRITE: 0x%x = 0x%x\n", reg, val); \
 	trace_i915_reg_rw(true, reg, val, sizeof(val)); \
 	if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 		__fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 10b92e8..fa016f8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1240,6 +1240,7 @@ SBI_WRITE(struct drm_i915_private *dev_priv, u16 reg, u32 value)
 			SBI_READY |
 			SBI_CTL_OP_CRWR);
 
+	DRM_DEBUG("SBI_WRITE: 0x%x = 0x%x\n", reg, value);
 	if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE)) == 0,
 				10))
 		DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
@@ -1265,6 +1266,7 @@ SBI_READ(struct drm_i915_private *dev_priv, u16 reg)
 
 	value = I915_READ(SBI_DATA);
 
+	DRM_DEBUG("SBI_READ: 0x%x = 0x%x\n", reg, value); \
 	return value;
 }
 
-- 
1.7.9.2

Re: [PATCH 01/37] drm/i915: add Haswell devices and their PCI IDs

[Daniel Vetter]

On Wed, Mar 21, 2012 at 10:09:36PM -0300, Eugeni Dodonov wrote:
> This adds product definitions for desktop, mobile and server boards.
> 
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

Like in the vlv series we need to split this into a second patch, which
just adds the pci ids to the tables, and which will get merged last when
everything works (well, works well enough).
-Daniel

> ---
>  drivers/char/agp/intel-agp.c    |    4 ++++
>  drivers/char/agp/intel-agp.h    |   11 +++++++++++
>  drivers/char/agp/intel-gtt.c    |   14 ++++++++++++++
>  drivers/gpu/drm/i915/i915_drv.c |   23 +++++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_drv.h |    2 ++
>  5 files changed, 54 insertions(+)
> 
> diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
> index 962e75d..0ad4933 100644
> --- a/drivers/char/agp/intel-agp.c
> +++ b/drivers/char/agp/intel-agp.c
> @@ -907,6 +907,10 @@ static struct pci_device_id agp_intel_pci_table[] = {
>  	ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB),
>  	ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB),
>  	ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB),
> +	ID(PCI_DEVICE_ID_INTEL_HASWELL_HB),
> +	ID(PCI_DEVICE_ID_INTEL_HASWELL_M_HB),
> +	ID(PCI_DEVICE_ID_INTEL_HASWELL_S_HB),
> +	ID(PCI_DEVICE_ID_INTEL_HASWELL_E_HB),
>  	{ }
>  };
>  
> diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
> index 5da67f1..46394c11 100644
> --- a/drivers/char/agp/intel-agp.h
> +++ b/drivers/char/agp/intel-agp.h
> @@ -234,6 +234,17 @@
>  #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG		0x0166
>  #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB		0x0158  /* Server */
>  #define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG		0x015A
> +#define PCI_DEVICE_ID_INTEL_HASWELL_HB				0x0400 /* Desktop */
> +#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG		0x0402
> +#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG		0x0412
> +#define PCI_DEVICE_ID_INTEL_HASWELL_M_HB			0x0404 /* Mobile */
> +#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG		0x0406
> +#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG		0x0416
> +#define PCI_DEVICE_ID_INTEL_HASWELL_S_HB			0x0408 /* Server */
> +#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG		0x040a
> +#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG		0x041a
> +#define PCI_DEVICE_ID_INTEL_HASWELL_SDV		0x0c16 /* SDV */
> +#define PCI_DEVICE_ID_INTEL_HASWELL_E_HB			0x0c04
>  
>  int intel_gmch_probe(struct pci_dev *pdev,
>  			       struct agp_bridge_data *bridge);
> diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
> index 5cf47ac..f494556 100644
> --- a/drivers/char/agp/intel-gtt.c
> +++ b/drivers/char/agp/intel-gtt.c
> @@ -1459,6 +1459,20 @@ static const struct intel_gtt_driver_description {
>  	    "Ivybridge", &sandybridge_gtt_driver },
>  	{ PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG,
>  	    "Ivybridge", &sandybridge_gtt_driver },
> +	{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG,
> +	    "Haswell", &sandybridge_gtt_driver },
> +	{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG,
> +	    "Haswell", &sandybridge_gtt_driver },
> +	{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG,
> +	    "Haswell", &sandybridge_gtt_driver },
> +	{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG,
> +	    "Haswell", &sandybridge_gtt_driver },
> +	{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG,
> +	    "Haswell", &sandybridge_gtt_driver },
> +	{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG,
> +	    "Haswell", &sandybridge_gtt_driver },
> +	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV,
> +	    "Haswell", &sandybridge_gtt_driver },
>  	{ 0, NULL, NULL }
>  };
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 0694e17..d4f542b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -248,6 +248,22 @@ static const struct intel_device_info intel_ivybridge_m_info = {
>  	.has_llc = 1,
>  };
>  
> +static const struct intel_device_info intel_haswell_d_info = {
> +	.is_haswell = 1, .gen = 7,
> +	.need_gfx_hws = 1, .has_hotplug = 1,
> +	.has_bsd_ring = 1,
> +	.has_blt_ring = 1,
> +	.has_llc = 1,
> +};
> +
> +static const struct intel_device_info intel_haswell_m_info = {
> +	.is_haswell = 1, .gen = 7, .is_mobile = 1,
> +	.need_gfx_hws = 1, .has_hotplug = 1,
> +	.has_bsd_ring = 1,
> +	.has_blt_ring = 1,
> +	.has_llc = 1,
> +};
> +
>  static const struct pci_device_id pciidlist[] = {		/* aka */
>  	INTEL_VGA_DEVICE(0x3577, &intel_i830_info),		/* I830_M */
>  	INTEL_VGA_DEVICE(0x2562, &intel_845g_info),		/* 845_G */
> @@ -292,6 +308,13 @@ static const struct pci_device_id pciidlist[] = {		/* aka */
>  	INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
>  	INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
>  	INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
> +	INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
> +	INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
> +	INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
> +	INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
> +	INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
> +	INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
> +	INTEL_VGA_DEVICE(0x0c16, &intel_haswell_d_info), /* SDV */
>  	{0, 0, 0}
>  };
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index c0f19f5..9a99ef1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -255,6 +255,7 @@ struct intel_device_info {
>  	u8 is_broadwater:1;
>  	u8 is_crestline:1;
>  	u8 is_ivybridge:1;
> +	u8 is_haswell:1;
>  	u8 has_fbc:1;
>  	u8 has_pipe_cxsr:1;
>  	u8 has_hotplug:1;
> @@ -1001,6 +1002,7 @@ struct drm_i915_file_private {
>  #define IS_IRONLAKE_D(dev)	((dev)->pci_device == 0x0042)
>  #define IS_IRONLAKE_M(dev)	((dev)->pci_device == 0x0046)
>  #define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)
> +#define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
>  #define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
>  
>  /*
> -- 
> 1.7.9.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 04/37] drm/i915: add haswell into the PCH SPLIT company

[Daniel Vetter]

On Wed, Mar 21, 2012 at 10:09:39PM -0300, Eugeni Dodonov wrote:
> Haswell is similar to Ivy Bridge in this sense.
> 
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

Given that vlv is gen7, too, but not pch_split, I think it's time to
promote this into a feature flag. We use this at tons of places, so the
added indirection imo isn't too bad.
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_drv.h |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fb50c42..51e04ec 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1047,7 +1047,7 @@ struct drm_i915_file_private {
>  #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
>  #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
>  
> -#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
> +#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
>  #define HAS_PLL_SPLIT(dev) (IS_IVYBRIDGE(dev))
>  #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
>  
> -- 
> 1.7.9.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 03/37] drm/i915: add HAS_PLL_SPLIT macro

[Daniel Vetter]

On Wed, Mar 21, 2012 at 10:09:38PM -0300, Eugeni Dodonov wrote:
> Ivy Bridge is the only GPU which has split 3-display support over 2 PLLs.
> 
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

This is imo a strange name for '3 pipes but just 2 plls' hw. And I
couldn't find any usage of this in your series, so I don't know how you
intend to use it. But usually for such narrow, single-chip special cases I
prefer a fe IS_IVB checks in the code instead of this indirection.
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_drv.h |    1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 49488e1..fb50c42 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1048,6 +1048,7 @@ struct drm_i915_file_private {
>  #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
>  
>  #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
> +#define HAS_PLL_SPLIT(dev) (IS_IVYBRIDGE(dev))
>  #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
>  
>  #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
> -- 
> 1.7.9.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 13/37] drm/i915: add support for SBI ops

[Daniel Vetter]

On Wed, Mar 21, 2012 at 10:09:48PM -0300, Eugeni Dodonov wrote:
> With Lynx Point, we need to use SBI to communicate with the display clock
> control. This commit adds helper functions to access the registers via
> SBI.
> 
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

Does this sbi stuff on hsw have anything to do with dpio from vlv? Or do
hw engineers simply like to reinvent the wheel?
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_display.c |   44 ++++++++++++++++++++++++++++++++++
>  1 file changed, 44 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index de1ba19..c225de4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1198,6 +1198,50 @@ static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
>  	POSTING_READ(reg);
>  }
>  
> +/* SBI access */
> +static inline void
> +SBI_WRITE(struct drm_i915_private *dev_priv, u16 reg, u32 value)
> +{
> +	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
> +				10))
> +		DRM_ERROR("timeout waiting for SBI to become ready\n");
> +
> +	I915_WRITE(SBI_ADDR,
> +			(reg << 16));
> +	I915_WRITE(SBI_DATA,
> +			value);
> +	I915_WRITE(SBI_CTL_STAT,
> +			SBI_READY |
> +			SBI_CTL_OP_CRWR);
> +
> +	if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE)) == 0,
> +				10))
> +		DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
> +}
> +
> +static inline u32
> +SBI_READ(struct drm_i915_private *dev_priv, u16 reg)
> +{
> +	u32 value;
> +	if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
> +				10))
> +		DRM_ERROR("timeout waiting for SBI to become ready\n");
> +
> +	I915_WRITE(SBI_ADDR,
> +			(reg << 16));
> +	I915_WRITE(SBI_CTL_STAT,
> +			SBI_READY |
> +			SBI_CTL_OP_CRRD);
> +
> +	if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE)) == 0,
> +				10))
> +		DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
> +
> +	value = I915_READ(SBI_DATA);
> +
> +	return value;
> +}
> +
>  /**
>   * intel_enable_pch_pll - enable PCH PLL
>   * @dev_priv: i915 private structure
> -- 
> 1.7.9.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 23/37] drm/i915: do not set 6BPP dithering on haswell

[Daniel Vetter]

On Wed, Mar 21, 2012 at 10:09:58PM -0300, Eugeni Dodonov wrote:
> We don't have those bits on Haswell anymore, so do not set them.
> 
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

Hm, how is 6bpp dithering supposed to work now, when e.g. a lame dp link
can't handle more due to bandwidth issues?
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_display.c |    5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index e056c32..24a0a6c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5335,9 +5335,10 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>  	pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
>  	if (is_dp) {
>  		if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
> -			pipeconf |= PIPECONF_BPP_6 |
> -				    PIPECONF_DITHER_EN |
> +			pipeconf |= PIPECONF_DITHER_EN |
>  				    PIPECONF_DITHER_TYPE_SP;
> +			if (!IS_HASWELL(dev))
> +				pipeconf |= PIPECONF_BPP_6;
>  		}
>  	}
>  
> -- 
> 1.7.9.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 26/37] drm/i915: reuse Ivybridge interrupts code for Haswell

[Daniel Vetter]

On Wed, Mar 21, 2012 at 10:10:01PM -0300, Eugeni Dodonov wrote:
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

Hm, I have a feeling that some of these s/IS_IVB/IS_GEN7/ checks will
collide with the vlv code. I guess neither Jesse nor you have tried to
merge in each another's branch yet. This will be fun to sort out ;-)
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_irq.c |    6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index afd4e03..ede51f0 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1810,7 +1810,7 @@ static void ironlake_irq_preinstall(struct drm_device *dev)
>  
>  	INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
>  	INIT_WORK(&dev_priv->error_work, i915_error_work_func);
> -	if (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
> +	if (IS_GEN6(dev) || IS_GEN7(dev))
>  		INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
>  
>  	I915_WRITE(HWSTAM, 0xeffe);
> @@ -2136,7 +2136,7 @@ void intel_irq_init(struct drm_device *dev)
>  {
>  	dev->driver->get_vblank_counter = i915_get_vblank_counter;
>  	dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
> -	if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
> +	if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_GEN7(dev)) {
>  		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
>  		dev->driver->get_vblank_counter = gm45_get_vblank_counter;
>  	}
> @@ -2147,7 +2147,7 @@ void intel_irq_init(struct drm_device *dev)
>  		dev->driver->get_vblank_timestamp = NULL;
>  	dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
>  
> -	if (IS_IVYBRIDGE(dev)) {
> +	if (IS_GEN7(dev)) {
>  		/* Share pre & uninstall handlers with ILK/SNB */
>  		dev->driver->irq_handler = ivybridge_irq_handler;
>  		dev->driver->irq_preinstall = ironlake_irq_preinstall;
> -- 
> 1.7.9.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 35/37] drm/i915: program iCLKIP on Lynx Point

[Daniel Vetter]

On Wed, Mar 21, 2012 at 10:10:10PM -0300, Eugeni Dodonov wrote:
> The iCLKIP clock is used to drive the VGA pixel clock on the PCH. In order
> to do so, it must be programmed to properly do the clock ticks according
> to the divisor, phase direction, phase increments and a special auxiliary
> divisor for 20MHz clock.
> 
> Those values can be programmed individually, by doing some math; or we
> could use a pre-defined table of values for each modeset. For speed and
> simplification, the idea was to just adopt the table of valid pixel clocks
> and select the matching iCLKIP values from there.
> 
> As a possible idea for the future, it would be possible to add a fallback
> and calculate those values manually in case no match is found. But I don't
> think we'll encounter a mode not covered by those table, and VGA is pretty
> much going away in the future anyway.
> 
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

With stuff like this, intel_display.c has definitely grown into the
unmanageable territory. Along Jesse's suggestion I think it would make
sense to split out the pch and gmch modeset stuff into separate files (and
leave all the other things like initialization, clock gating watermark
functions, pageflip, cursors, power crap and what not else in
intel_display.c). We could call these new files intel_pch_modeset.c and
intel_gmch_modeset.c, they'd contain the respective crtc_mode_set function
plus all associated support code.

I'll leave this to you and Jesse to decide whether it makes sense as
proposed and when you want to move the code. But I think we need to
slaugther this dragon and cut it into more manageable pieces now.

Jesse?

Yours, Daniel

> ---
>  drivers/gpu/drm/i915/intel_display.c |  309 ++++++++++++++++++++++++++++++++++
>  1 file changed, 309 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 5f6cb35..a37e0b7 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2761,6 +2761,312 @@ static const long hsw_ddi_buf_ctl_values[] = {
>  	DDI_BUF_EMP_800MV_3_5DB_HSW
>  };
>  
> +/* Available pixel clock values */
> +struct iclk_vga_clock {
> +	u32 clock;
> +	u16 auxdiv;
> +	u16 divsel;
> +	u16 phasedir;
> +	u16 phaseinc;
> +};
> +
> +static const struct iclk_vga_clock iclk_vga_clock_table[] = {
> +	{20000,	1,	0x41,	0,	0x20},	/* 20000 ppm=0 */
> +	{21000,	0,	0x7E,	0,	0x25},	/* 20999 ppm=-53 */
> +	{21912,	0,	0x79,	0,	0x0E},	/* 21912 ppm=12 */
> +	{22000,	0,	0x78,	0,	0x2F},	/* 21999 ppm=-58 */
> +	{23000,	0,	0x73,	0,	0x19},	/* 23000 ppm=6 */
> +	{24000,	0,	0x6E,	0,	0x20},	/* 24000 ppm=0 */
> +	{25000,	0,	0x6A,	0,	0x00},	/* 25000 ppm=0 */
> +	{25175,	0,	0x69,	0,	0x10},	/* 25175 ppm=-7 */
> +	{25200,	0,	0x69,	0,	0x09},	/* 25201 ppm=21 */
> +	{26000,	0,	0x66,	1,	0x0A},	/* 26001 ppm=24 */
> +	{27000,	0,	0x62,	0,	0x00},	/* 27000 ppm=0 */
> +	{27027,	0,	0x62,	1,	0x06},	/* 27025 ppm=-62 */
> +	{27500,	0,	0x60,	0,	0x0C},	/* 27498 ppm=-58 */
> +	{28000,	0,	0x5E,	0,	0x1B},	/* 28002 ppm=70 */
> +	{28320,	0,	0x5D,	0,	0x16},	/* 28319 ppm=-50 */
> +	{28322,	0,	0x5D,	0,	0x15},	/* 28323 ppm=44 */
> +	{29000,	0,	0x5B,	0,	0x07},	/* 28998 ppm=-64 */
> +	{30000,	0,	0x58,	0,	0x00},	/* 30000 ppm=0 */
> +	{31000,	0,	0x55,	0,	0x06},	/* 31001 ppm=35 */
> +	{31500,	0,	0x54,	1,	0x12},	/* 31498 ppm=-53 */
> +	{32000,	0,	0x52,	0,	0x18},	/* 32000 ppm=0 */
> +	{32500,	0,	0x51,	0,	0x05},	/* 32500 ppm=-15 */
> +	{33000,	0,	0x50,	1,	0x0C},	/* 33002 ppm=70 */
> +	{34000,	0,	0x4D,	0,	0x1A},	/* 34002 ppm=70 */
> +	{35000,	0,	0x4B,	0,	0x09},	/* 35001 ppm=29 */
> +	{35500,	0,	0x4A,	0,	0x04},	/* 35497 ppm=-82 */
> +	{36000,	0,	0x49,	0,	0x00},	/* 36000 ppm=0 */
> +	{37000,	0,	0x47,	1,	0x02},	/* 37002 ppm=58 */
> +	{38000,	0,	0x45,	0,	0x03},	/* 38003 ppm=82 */
> +	{39000,	0,	0x43,	0,	0x0F},	/* 38998 ppm=-53 */
> +	{40000,	0,	0x41,	0,	0x20},	/* 40000 ppm=0 */
> +	{40500,	0,	0x41,	1,	0x15},	/* 40497 ppm=-79 */
> +	{40541,	0,	0x41,	1,	0x1A},	/* 40544 ppm=95 */
> +	{41000,	0,	0x40,	1,	0x09},	/* 40996 ppm=-87 */
> +	{41540,	0,	0x3F,	0,	0x00},	/* 41538 ppm=-38 */
> +	{42000,	0,	0x3E,	0,	0x12},	/* 42003 ppm=70 */
> +	{43000,	0,	0x3D,	1,	0x0D},	/* 42996 ppm=-99 */
> +	{43163,	0,	0x3D,	1,	0x1D},	/* 43168 ppm=108 */
> +	{44000,	0,	0x3B,	0,	0x17},	/* 44003 ppm=70 */
> +	{44900,	0,	0x3A,	0,	0x09},	/* 44895 ppm=-117 */
> +	{45000,	0,	0x3A,	0,	0x00},	/* 45000 ppm=0 */
> +	{46000,	0,	0x39,	1,	0x13},	/* 45994 ppm=-128 */
> +	{47000,	0,	0x37,	0,	0x1D},	/* 46995 ppm=-110 */
> +	{48000,	0,	0x36,	0,	0x10},	/* 48000 ppm=0 */
> +	{49000,	0,	0x35,	0,	0x07},	/* 48993 ppm=-134 */
> +	{49500,	0,	0x35,	1,	0x1D},	/* 49499 ppm=-27 */
> +	{50000,	0,	0x34,	0,	0x00},	/* 50000 ppm=0 */
> +	{51000,	0,	0x33,	1,	0x04},	/* 51004 ppm=70 */
> +	{52000,	0,	0x32,	1,	0x05},	/* 52001 ppm=24 */
> +	{52406,	0,	0x32,	1,	0x1F},	/* 52411 ppm=101 */
> +	{53000,	0,	0x31,	1,	0x04},	/* 53006 ppm=116 */
> +	{54000,	0,	0x30,	0,	0x00},	/* 54000 ppm=0 */
> +	{54054,	0,	0x30,	1,	0x03},	/* 54051 ppm=-62 */
> +	{55000,	0,	0x2F,	0,	0x06},	/* 54997 ppm=-58 */
> +	{56000,	0,	0x2E,	0,	0x0E},	/* 55995 ppm=-93 */
> +	{56250,	0,	0x2E,	0,	0x00},	/* 56250 ppm=0 */
> +	{57000,	0,	0x2D,	0,	0x18},	/* 56992 ppm=-139 */
> +	{58000,	0,	0x2D,	1,	0x1D},	/* 58006 ppm=105 */
> +	{59000,	0,	0x2C,	1,	0x0F},	/* 58996 ppm=-64 */
> +	{60000,	0,	0x2B,	0,	0x00},	/* 60000 ppm=0 */
> +	{61000,	0,	0x2A,	0,	0x11},	/* 60995 ppm=-76 */
> +	{62000,	0,	0x2A,	1,	0x1D},	/* 62002 ppm=35 */
> +	{63000,	0,	0x29,	1,	0x09},	/* 62997 ppm=-53 */
> +	{64000,	0,	0x28,	0,	0x0C},	/* 64000 ppm=0 */
> +	{65000,	0,	0x28,	1,	0x1E},	/* 65011 ppm=174 */
> +	{66000,	0,	0x27,	1,	0x06},	/* 66005 ppm=70 */
> +	{66667,	0,	0x26,	0,	0x20},	/* 66667 ppm=-5 */
> +	{67000,	0,	0x26,	0,	0x13},	/* 67003 ppm=41 */
> +	{68000,	0,	0x26,	1,	0x13},	/* 68005 ppm=70 */
> +	{68179,	0,	0x26,	1,	0x19},	/* 68166 ppm=-196 */
> +	{69000,	0,	0x25,	0,	0x08},	/* 69010 ppm=139 */
> +	{70000,	0,	0x25,	1,	0x1B},	/* 69988 ppm=-174 */
> +	{71000,	0,	0x24,	0,	0x02},	/* 70994 ppm=-82 */
> +	{72000,	0,	0x23,	0,	0x20},	/* 72000 ppm=0 */
> +	{73000,	0,	0x23,	1,	0x01},	/* 73004 ppm=53 */
> +	{74000,	0,	0x22,	0,	0x1F},	/* 74004 ppm=58 */
> +	{74175,	0,	0x22,	0,	0x1A},	/* 74163 ppm=-161 */
> +	{74250,	0,	0x22,	0,	0x17},	/* 74259 ppm=118 */
> +	{74481,	0,	0x22,	0,	0x10},	/* 74483 ppm=24 */
> +	{75000,	0,	0x22,	0,	0x00},	/* 75000 ppm=0 */
> +	{76000,	0,	0x22,	1,	0x1E},	/* 75989 ppm=-139 */
> +	{77000,	0,	0x21,	0,	0x04},	/* 77005 ppm=70 */
> +	{78000,	0,	0x21,	1,	0x19},	/* 78014 ppm=174 */
> +	{78750,	0,	0x20,	0,	0x12},	/* 78760 ppm=131 */
> +	{79000,	0,	0x20,	0,	0x0B},	/* 79012 ppm=157 */
> +	{80000,	0,	0x20,	1,	0x10},	/* 80000 ppm=0 */
> +	{81000,	0,	0x1F,	0,	0x15},	/* 81013 ppm=157 */
> +	{81081,	0,	0x1F,	0,	0x13},	/* 81089 ppm=95 */
> +	{81624,	0,	0x1F,	0,	0x05},	/* 81625 ppm=12 */
> +	{82000,	0,	0x1F,	1,	0x05},	/* 82012 ppm=151 */
> +	{83000,	0,	0x1F,	1,	0x1E},	/* 82997 ppm=-35 */
> +	{83950,	0,	0x1E,	0,	0x0A},	/* 83965 ppm=179 */
> +	{84000,	0,	0x1E,	0,	0x09},	/* 84006 ppm=70 */
> +	{85000,	0,	0x1E,	1,	0x0F},	/* 84998 ppm=-29 */
> +	{86000,	0,	0x1D,	0,	0x19},	/* 86013 ppm=151 */
> +	{87000,	0,	0x1D,	0,	0x02},	/* 87009 ppm=105 */
> +	{88000,	0,	0x1D,	1,	0x14},	/* 87984 ppm=-186 */
> +	{89000,	0,	0x1C,	0,	0x16},	/* 88980 ppm=-220 */
> +	{90000,	0,	0x1C,	0,	0x00},	/* 90000 ppm=0 */
> +	{91000,	0,	0x1C,	1,	0x15},	/* 90995 ppm=-53 */
> +	{92000,	0,	0x1B,	0,	0x16},	/* 92013 ppm=139 */
> +	{93000,	0,	0x1B,	0,	0x02},	/* 93003 ppm=35 */
> +	{94000,	0,	0x1B,	1,	0x12},	/* 94015 ppm=163 */
> +	{94500,	0,	0x1B,	1,	0x1B},	/* 94478 ppm=-235 */
> +	{95000,	0,	0x1A,	0,	0x1B},	/* 94997 ppm=-29 */
> +	{95654,	0,	0x1A,	0,	0x0F},	/* 95628 ppm=-271 */
> +	{96000,	0,	0x1A,	0,	0x08},	/* 96000 ppm=0 */
> +	{97000,	0,	0x1A,	1,	0x0B},	/* 97024 ppm=249 */
> +	{98000,	0,	0x1A,	1,	0x1D},	/* 98015 ppm=151 */
> +	{99000,	0,	0x19,	0,	0x11},	/* 99026 ppm=261 */
> +	{100000,	0,	0x19,	0,	0x00},	/* 100000 ppm=0 */
> +	{101000,	0,	0x19,	1,	0x11},	/* 100994 ppm=-64 */
> +	{102000,	0,	0x18,	0,	0x1E},	/* 102007 ppm=70 */
> +	{103000,	0,	0x18,	0,	0x0E},	/* 102980 ppm=-197 */
> +	{104000,	0,	0x18,	1,	0x02},	/* 103971 ppm=-278 */
> +	{105000,	0,	0x18,	1,	0x12},	/* 104982 ppm=-174 */
> +	{106000,	0,	0x17,	0,	0x1E},	/* 106012 ppm=116 */
> +	{107000,	0,	0x17,	0,	0x0F},	/* 106997 ppm=-29 */
> +	{107214,	0,	0x17,	0,	0x0C},	/* 107196 ppm=-168 */
> +	{108000,	0,	0x17,	0,	0x00},	/* 108000 ppm=0 */
> +	{109000,	0,	0x17,	1,	0x0F},	/* 109022 ppm=203 */
> +	{110000,	0,	0x17,	1,	0x1D},	/* 109994 ppm=-58 */
> +	{110013,	0,	0x17,	1,	0x1D},	/* 109994 ppm=-177 */
> +	{111000,	0,	0x16,	0,	0x15},	/* 110983 ppm=-157 */
> +	{111263,	0,	0x16,	0,	0x11},	/* 111269 ppm=55 */
> +	{111375,	0,	0x16,	0,	0x10},	/* 111340 ppm=-313 */
> +	{112000,	0,	0x16,	0,	0x07},	/* 111990 ppm=-93 */
> +	{113000,	0,	0x16,	1,	0x07},	/* 113015 ppm=134 */
> +	{113309,	0,	0x16,	1,	0x0B},	/* 113311 ppm=22 */
> +	{113100,	0,	0x16,	1,	0x08},	/* 113089 ppm=-98 */
> +	{114000,	0,	0x16,	1,	0x14},	/* 113984 ppm=-139 */
> +	{115000,	0,	0x15,	0,	0x1F},	/* 114970 ppm=-261 */
> +	{116000,	0,	0x15,	0,	0x12},	/* 115973 ppm=-232 */
> +	{117000,	0,	0x15,	0,	0x05},	/* 116994 ppm=-53 */
> +	{118000,	0,	0x15,	1,	0x08},	/* 118033 ppm=278 */
> +	{119000,	0,	0x15,	1,	0x14},	/* 119008 ppm=70 */
> +	{119651,	0,	0x15,	1,	0x1C},	/* 119668 ppm=139 */
> +	{120000,	0,	0x14,	0,	0x20},	/* 120000 ppm=0 */
> +	{121000,	0,	0x14,	0,	0x14},	/* 121008 ppm=70 */
> +	{122000,	0,	0x14,	0,	0x08},	/* 122034 ppm=278 */
> +	{122614,	0,	0x14,	0,	0x01},	/* 122640 ppm=214 */
> +	{123000,	0,	0x14,	1,	0x03},	/* 122989 ppm=-87 */
> +	{123379,	0,	0x14,	1,	0x07},	/* 123340 ppm=-313 */
> +	{124000,	0,	0x14,	1,	0x0E},	/* 123960 ppm=-324 */
> +	{125000,	0,	0x14,	1,	0x1A},	/* 125036 ppm=290 */
> +	{126000,	0,	0x13,	0,	0x1B},	/* 126039 ppm=313 */
> +	{127000,	0,	0x13,	0,	0x11},	/* 126965 ppm=-272 */
> +	{128000,	0,	0x13,	0,	0x06},	/* 128000 ppm=0 */
> +	{129000,	0,	0x13,	1,	0x04},	/* 128955 ppm=-348 */
> +	{129859,	0,	0x13,	1,	0x0D},	/* 129827 ppm=-245 */
> +	{130000,	0,	0x13,	1,	0x0F},	/* 130023 ppm=174 */
> +	{131000,	0,	0x13,	1,	0x19},	/* 131008 ppm=64 */
> +	{131850,	0,	0x12,	0,	0x1F},	/* 131808 ppm=-321 */
> +	{132000,	0,	0x12,	0,	0x1D},	/* 132009 ppm=70 */
> +	{133000,	0,	0x12,	0,	0x13},	/* 133025 ppm=192 */
> +	{133330,	0,	0x12,	0,	0x10},	/* 133333 ppm=26 */
> +	{134000,	0,	0x12,	0,	0x0A},	/* 133953 ppm=-348 */
> +	{135000,	0,	0x12,	0,	0x00},	/* 135000 ppm=0 */
> +	{136000,	0,	0x12,	1,	0x09},	/* 135956 ppm=-324 */
> +	{137000,	0,	0x12,	1,	0x13},	/* 137034 ppm=249 */
> +	{138000,	0,	0x12,	1,	0x1C},	/* 138019 ppm=139 */
> +	{139000,	0,	0x11,	0,	0x1B},	/* 139019 ppm=134 */
> +	{139050,	0,	0x11,	0,	0x1B},	/* 139019 ppm=-227 */
> +	{139054,	0,	0x11,	0,	0x1B},	/* 139019 ppm=-256 */
> +	{140000,	0,	0x11,	0,	0x12},	/* 140032 ppm=232 */
> +	{141000,	0,	0x11,	0,	0x0A},	/* 140946 ppm=-382 */
> +	{142000,	0,	0x11,	0,	0x01},	/* 141988 ppm=-82 */
> +	{143000,	0,	0x11,	1,	0x08},	/* 143046 ppm=325 */
> +	{143472,	0,	0x11,	1,	0x0C},	/* 143522 ppm=346 */
> +	{144000,	0,	0x11,	1,	0x10},	/* 144000 ppm=0 */
> +	{145000,	0,	0x11,	1,	0x18},	/* 144966 ppm=-232 */
> +	{146000,	0,	0x10,	0,	0x20},	/* 145946 ppm=-371 */
> +	{147000,	0,	0x10,	0,	0x18},	/* 146939 ppm=-417 */
> +	{147891,	0,	0x10,	0,	0x10},	/* 147945 ppm=367 */
> +	{148000,	0,	0x10,	0,	0x10},	/* 147945 ppm=-371 */
> +	{148350,	0,	0x10,	0,	0x0D},	/* 148326 ppm=-161 */
> +	{148500,	0,	0x10,	0,	0x0C},	/* 148454 ppm=-313 */
> +	{149000,	0,	0x10,	0,	0x08},	/* 148966 ppm=-232 */
> +	{150000,	0,	0x10,	0,	0x00},	/* 150000 ppm=0 */
> +	{151000,	0,	0x10,	1,	0x08},	/* 151049 ppm=325 */
> +	{152000,	0,	0x10,	1,	0x0F},	/* 151979 ppm=-139 */
> +	{152280,	0,	0x10,	1,	0x11},	/* 152247 ppm=-219 */
> +	{153000,	0,	0x10,	1,	0x17},	/* 153056 ppm=365 */
> +	{154000,	0,	0x10,	1,	0x1E},	/* 154011 ppm=70 */
> +	{155000,	0,	0x0F,	0,	0x1B},	/* 154978 ppm=-145 */
> +	{156000,	0,	0x0F,	0,	0x14},	/* 155957 ppm=-278 */
> +	{157000,	0,	0x0F,	0,	0x0D},	/* 156948 ppm=-330 */
> +	{157500,	0,	0x0F,	0,	0x09},	/* 157521 ppm=131 */
> +	{158000,	0,	0x0F,	0,	0x06},	/* 157952 ppm=-301 */
> +	{159000,	0,	0x0F,	1,	0x01},	/* 158970 ppm=-191 */
> +	{160000,	0,	0x0F,	1,	0x08},	/* 160000 ppm=0 */
> +	{161000,	0,	0x0F,	1,	0x0F},	/* 161044 ppm=273 */
> +	{162000,	0,	0x0F,	1,	0x15},	/* 161949 ppm=-313 */
> +	{163000,	0,	0x0F,	1,	0x1C},	/* 163019 ppm=116 */
> +	{164000,	0,	0x0E,	0,	0x1E},	/* 163947 ppm=-324 */
> +	{165000,	0,	0x0E,	0,	0x17},	/* 165043 ppm=261 */
> +	{166000,	0,	0x0E,	0,	0x11},	/* 165994 ppm=-35 */
> +	{167000,	0,	0x0E,	0,	0x0B},	/* 166957 ppm=-261 */
> +	{168000,	0,	0x0E,	0,	0x05},	/* 167930 ppm=-417 */
> +	{169000,	0,	0x0E,	1,	0x02},	/* 169080 ppm=475 */
> +	{169128,	0,	0x0E,	1,	0x02},	/* 169080 ppm=-283 */
> +	{170000,	0,	0x0E,	1,	0x08},	/* 170079 ppm=464 */
> +	{171000,	0,	0x0E,	1,	0x0D},	/* 170920 ppm=-469 */
> +	{172000,	0,	0x0E,	1,	0x13},	/* 171940 ppm=-348 */
> +	{172800,	0,	0x0E,	1,	0x18},	/* 172800 ppm=0 */
> +	{173000,	0,	0x0E,	1,	0x19},	/* 172973 ppm=-157 */
> +	{174000,	0,	0x0E,	1,	0x1F},	/* 174018 ppm=105 */
> +	{174787,	0,	0x0D,	0,	0x1D},	/* 174722 ppm=-373 */
> +	{175000,	0,	0x0D,	0,	0x1B},	/* 175076 ppm=435 */
> +	{175500,	0,	0x0D,	0,	0x19},	/* 175431 ppm=-391 */
> +	{176000,	0,	0x0D,	0,	0x16},	/* 175967 ppm=-186 */
> +	{177000,	0,	0x0D,	0,	0x10},	/* 177049 ppm=278 */
> +	{178000,	0,	0x0D,	0,	0x0B},	/* 177961 ppm=-220 */
> +	{179000,	0,	0x0D,	0,	0x05},	/* 179067 ppm=377 */
> +	{180000,	0,	0x0D,	0,	0x00},	/* 180000 ppm=0 */
> +};
> +
> +/* Program iCLKIP clock to the desired frequency */
> +static void lpt_program_iclkip(struct drm_crtc *crtc)
> +{
> +	struct drm_device *dev = crtc->dev;
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	u32 auxdiv=0, divsel=0, phasedir=0, phaseinc=0, valid=0;
> +	u32 temp, i;
> +
> +	/* Ungate pixel clock */
> +	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
> +
> +	/* Disable SSCCTL */
> +	SBI_WRITE(dev_priv, SBI_SSCCTL6,
> +				SBI_READ(dev_priv, SBI_SSCCTL6) |
> +					SBI_SSCCTL_DISABLE);
> +
> +	/* Calculating clock values for iCLKIP */
> +	for (i=0; i < ARRAY_SIZE(iclk_vga_clock_table); i++) {
> +		if (crtc->mode.clock == iclk_vga_clock_table[i].clock) {
> +			DRM_INFO("Found clock settings for %dKHz refresh rate\n",
> +					crtc->mode.clock);
> +
> +			auxdiv = iclk_vga_clock_table[i].auxdiv;
> +			divsel = iclk_vga_clock_table[i].divsel;
> +			phasedir = iclk_vga_clock_table[i].phasedir;
> +			phaseinc = iclk_vga_clock_table[i].phaseinc;
> +
> +			valid = 1;
> +
> +			break;
> +		}
> +	}
> +
> +	if (!valid) {
> +		DRM_ERROR("Unable to find iCLKIP clock settings for %dKHz refresh rate\n",
> +				crtc->mode.clock);
> +		return;
> +	}
> +
> +	/* Program SSCDIVINTPHASE6 with values which HW team uses */
> +	DRM_DEBUG("Programming SSCDIVINTPHASE for %dKHz: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
> +			crtc->mode.clock,
> +			auxdiv,
> +			divsel,
> +			phasedir,
> +			phaseinc);
> +
> +	/* Program SSCDIVINTPHASE6 */
> +	temp = SBI_READ(dev_priv, SBI_SSCDIVINTPHASE6);
> +	temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
> +	temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
> +	temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
> +	temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
> +	temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
> +	temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
> +
> +	SBI_WRITE(dev_priv,
> +			SBI_SSCDIVINTPHASE6,
> +			temp);
> +
> +	/* Program SSCAUXDIV */
> +	SBI_WRITE(dev_priv,
> +			SBI_SSCAUXDIV6,
> +				SBI_READ(dev_priv, SBI_SSCAUXDIV6) |
> +					SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv));
> +
> +
> +	/* Enable modulator and associated divider */
> +	SBI_WRITE(dev_priv, SBI_SSCCTL6,
> +				SBI_READ(dev_priv, SBI_SSCCTL6) &
> +					~SBI_SSCCTL_DISABLE);
> +
> +	/* Wait for initialization time */
> +	udelay(50);
> +
> +	/* Gate pixel clock */
> +	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
> +}
> +
>  
>  /* Link training for HSW parts */
>  static void hsw_fdi_link_train(struct drm_crtc *crtc)
> @@ -3182,6 +3488,9 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>  		/* DDIE clock is recommented for FDI connections */
>  		I915_WRITE(PIPE_CLK_SEL(pipe),
>  				PIPE_CLK_SEL_DDIE);
> +
> +		/* Program iCLKIP */
> +		lpt_program_iclkip(crtc);
>  	}
>  
>  	/* set transcoder timing, panel must allow it */
> -- 
> 1.7.9.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 07/37] drm/i915: add DP_TP_CTL registers

[Chris Wilson]

On Wed, 21 Mar 2012 22:09:42 -0300, Eugeni Dodonov <eugeni.dodonov@intel.com> wrote:
> This is one set of those registers for each pipe.
> 
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |   16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 09b2267..7a9232e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3890,4 +3890,20 @@
>  #define  PIPE_DDI_PORT_WIDTH_X2			(1<<1)
>  #define  PIPE_DDI_PORT_WIDTH_X4			(3<<1)
>  
> +/* DisplayPort Transport Control */
> +#define DP_TP_CTL_A			0x64040
> +#define DP_TP_CTL_B			0x64140
> +#define DP_TP_CTL_C			0x64240
> +#define DP_TP_CTL_D			0x64340
> +#define DP_TP_CTL_E			0x64440
> +#define  DP_TP_CTL_ENABLE		(1<<31)
> +#define  DP_TP_CTL_MODE_SST	(0<<27)
> +#define  DP_TP_CTL_MODE_MST	(1<<27)
> +#define  DP_TP_CTL_ENHANCED_FRAME_ENABLE	(1<<18)
> +#define  DP_TP_CTL_FDI_AUTOTRAIN	(1<<15)
> +#define  DP_TP_CTL_LINK_TRAIN_MASK		(7<<8)
> +#define  DP_TP_CTL_LINK_TRAIN_PAT1		(0<<8)
> +#define  DP_TP_CTL_LINK_TRAIN_PAT2		(1<<8)
> +#define  DP_TP_CTL_LINK_TRAIN_NORMAL	(3<<8)

Would these not benefit from a #define DP_TP_CTL(pipe)?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 08/37] drm/i915: add DP_TP_STATUS registers

[Chris Wilson]

On Wed, 21 Mar 2012 22:09:43 -0300, Eugeni Dodonov <eugeni.dodonov@intel.com> wrote:
> There is one set of those registers for each port.

Looks like we need an enum port in addition to enum plane and enum pipe.
And a _PORT() switcher. The idea behind having separate PIPE, PLANE,
PORT macros was that eventually we would put a
BUILD_BUG_ON(typeof(&x)!=typeof(enum pipe *)) and so catch misuse of
pipe versus plane (a common bug in the bad old days). However, that
requires the code base being cleansed of all the int plane, port;
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 13/37] drm/i915: add support for SBI ops

[Chris Wilson]

On Wed, 21 Mar 2012 22:09:48 -0300, Eugeni Dodonov <eugeni.dodonov@intel.com> wrote:
> With Lynx Point, we need to use SBI to communicate with the display clock
> control. This commit adds helper functions to access the registers via
> SBI.
> 
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |   44 ++++++++++++++++++++++++++++++++++
>  1 file changed, 44 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index de1ba19..c225de4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1198,6 +1198,50 @@ static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
>  	POSTING_READ(reg);
>  }
>  
> +/* SBI access */
> +static inline void
> +SBI_WRITE(struct drm_i915_private *dev_priv, u16 reg, u32 value)

These are too big and too frequent to be inlined. At least that means we
won't have to shout!
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [RFC] [PATCH 00/38] Haswell

[Daniel Vetter]

On Wed, Mar 21, 2012 at 10:09:35PM -0300, Eugeni Dodonov wrote:
> Hi folks,
> 
> To contribute to everyones curiosity and further enrich Phoronix articles
> :), this is the initial Haswell enablement patchset for basic modesetting
> support over VGA.
> 
> This is actually the first time I am doing such enablement, and the
> combination of HSW/LPT changes proved to be quite tricky, yet also very cool
> to do. But certainly, while I tried to split the patches in the best way to
> 'tell a story', I suspect lots and lots of things could be improved. So
> bikeshedding is much welcomed! And of course, there are still a bunch of
> things missing, but those can be done in parallel now.
> 
> As for those patches, I organized them in the following way:
>  - The first part adds new hardware information and new registers which we'll
>    need to make it work (a.k.a, 'The Pledge'). This goes from patch 01 until
>    patch 21.
>  - The second part does small changes to existent functions to make them work
>    on Haswell ('The Turn'). This goes from patch 22 to patch 28.  Haswell is
>    not quite Gen7, but is shares lots of stuff with what we already have, so
>    there was no point in reinventing the wheel just now.
>  - The third part makes things work by enabling power wells, DDI and FDI
>    connections, PCH-specific stuff and so on ('The Prestige'). This is from
>    patch 29 to patch 35. Those are the scariest ones, but I couldn't split them
>    better and still maintain logical consistency among them.  Initially, those
>    were 24 small patches, but it was very hard to keep track of them, so I
>    combined them into just 6 for this patchset.
>  - And finally, there are 2 last patches ('The Prestige Debug' :)) which won't
>    be present in the final series, but are helpful at least for me to trace
>    where things go wrong. So if you run into issues and want to send me a
>    dmesg, those traces will make my life so much easier.
> 
> I didn't wanted to go much deeper with HSW for now because I would end up
> doing a massive code reordering to maintain my mental sanity, and as we
> already discussed by email earlier today Jesse is running into same problems
> as well. So perhaps we should just settle on doing some cleanup in our
> intel_display module before adding more platform-specific stuff?

Awesome work and nice patch series. To satisfy you're expectation, I've
dropped a few bikesheds on it. Now my gut says that this needs some more
work before we can merge hsw support, but there are quite a few things
that I'd like to pick up earlier (just so you don't have to carry so many
patches):

- the separate register definition patches are rather nice, so as soon as
  someone with enough coffee has cross-checked them with Bspec I could
  merge them, maybe already next week.

- some of the infrastucture work (like adding the has_pch_split feature
  work) could go in early, too. Luckily hsw seems to be less a
  frankenstein monster than vlv, which nicely reflects in much fewer pain
  points when integrating it in our code.

- for merging real hsw support (and especially the pci ids) I think we
  should wait until digital outputs also work somewhat.

Yours, Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 18/37] drm/i915: add GTC registers

[Chris Wilson]

On Wed, 21 Mar 2012 22:09:53 -0300, Eugeni Dodonov <eugeni.dodonov@intel.com> wrote:
> Add Global Time Clock registers

Interesting; driven by what? Is it coupled to the EU? Will it fail along
with the GPU or is an external source?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 21/37] drm/i915: calculate watermarks on Gen7 archs in one place

[Chris Wilson]

On Wed, 21 Mar 2012 22:09:56 -0300, Eugeni Dodonov <eugeni.dodonov@intel.com> wrote:
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index c225de4..46633fe 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4649,7 +4649,7 @@ void sandybridge_update_wm(struct drm_device *dev)
>  	}
>  
>  	/* IVB has 3 pipes */
> -	if (IS_IVYBRIDGE(dev) &&
> +	if (IS_GEN7(dev) &&

I can sense a Jesse rant about needing proper names to distinguish gen7
render engines versus gen7 displays. But maybe another time. ;-)
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 22/37] drm/i915: program WM_LINETIME on Haswell

[Chris Wilson]

On Wed, 21 Mar 2012 22:09:57 -0300, Eugeni Dodonov <eugeni.dodonov@intel.com> wrote:
> The line time can be programmed according to the number of horizontal
> pixels vs effective pixel rate ratio.
> 
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |   11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 46633fe..e056c32 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6073,6 +6073,17 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
>  		   (adjusted_mode->crtc_vsync_start - 1) |
>  		   ((adjusted_mode->crtc_vsync_end - 1) << 16));
>  
> +	if (IS_HASWELL(dev)) {
> +		temp = I915_READ(PIPE_WM_LINETIME(pipe));
> +		temp &= ~PIPE_WM_LINETIME_LINETIME_MASK;
> +
> +		/* Pipe horizontal total number of pixels / pixel rate in MHz. */
That comment really doesn't tell me anything more than the following
line. Ok, perhaps a CLOCK_TO_MHz(x) ((x)/1000), but not a lot else.
/* The WM are automatically computed based on how long it takes to fill a row at the given clock rate */
is slightly better as to start to see the meaning and the why.

Any chance of finding another name for LINETIME, perhaps duration:
PIPE_WM_LINETIME_MASK
PIPE_WM_LINETIME_TIME(x)
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 29/37] drm/i915: enable power wells on haswell init

[Chris Wilson]

On Wed, 21 Mar 2012 22:10:04 -0300, Eugeni Dodonov <eugeni.dodonov@intel.com> wrote:
> This attempts to enable all the available power wells during the
> initialization.
> 
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |   31 +++++++++++++++++++++++++++++++
>  1 file changed, 31 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3b3dc15..2c5b953 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9142,6 +9142,34 @@ static void i915_disable_vga(struct drm_device *dev)
>  	POSTING_READ(vga_reg);
>  }
>  
> +/* Starting with Haswell, we have different power wells for
> + * different parts of the GPU. This attempts to enable them all.
> + */
> +static void intel_init_power_wells(struct drm_device *dev)
> +{
> +	struct drm_i915_private *dev_priv = dev->dev_private;
> +	unsigned long power_wells[] = {
> +		HSW_PWR_WELL_CTL1,
> +		HSW_PWR_WELL_CTL2,
> +		HSW_PWR_WELL_CTL4
> +	};
> +	int i;
> +
> +	mutex_lock(&dev->struct_mutex);
> +
> +	for (i = 0; i < ARRAY_SIZE(power_wells); i++) {
> +		int well = I915_READ(power_wells[i]);
> +
> +		if ((well & HSW_PWR_WELL_STATE) == 0) {
> +			I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
> +			if (wait_for(I915_READ(power_wells[i] & HSW_PWR_WELL_STATE), 20))
> +				DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);
> +		}
> +	}

Out of curiosity, can we enable the powerwells in parallel or must it be
done sequentially?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 31/37] drm/i915: enable PCH earlier

[Chris Wilson]

On Wed, 21 Mar 2012 22:10:06 -0300, Eugeni Dodonov <eugeni.dodonov@intel.com> wrote:
> The modesetting sequence for PCH-related connections mentions that the
> order of plane/pipe enablement could happen either before of after PCH
> enablement.
> 
> With LPT, however, we need to enable some things earlier to be able to
> talk to PCH. So let's do it a bit in advance.

Touching modesetting sequence is a nerve racking experience. Can we
arrange to have this patch tested by itself, right now?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 21/37] drm/i915: calculate watermarks on Gen7 archs in one place

[Daniel Vetter]

On Thu, Mar 22, 2012 at 10:52:50AM +0000, Chris Wilson wrote:
> On Wed, 21 Mar 2012 22:09:56 -0300, Eugeni Dodonov <eugeni.dodonov@intel.com> wrote:
> > Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c |    2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index c225de4..46633fe 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4649,7 +4649,7 @@ void sandybridge_update_wm(struct drm_device *dev)
> >  	}
> >  
> >  	/* IVB has 3 pipes */
> > -	if (IS_IVYBRIDGE(dev) &&
> > +	if (IS_GEN7(dev) &&
> 
> I can sense a Jesse rant about needing proper names to distinguish gen7
> render engines versus gen7 displays. But maybe another time. ;-)

You already have a Daniel rant somewhere later complaining that some of
the s/IS_IVB/IS_GEN7/ will surely blow up on vlv ;-)
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 37/37] drm/i915: dump registers read/write ops

[Chris Wilson]

On Wed, 21 Mar 2012 22:10:12 -0300, Eugeni Dodonov <eugeni.dodonov@intel.com> wrote:
> This logs all the registers and SBI accesses as they happen.
> 
> Note that it is not supposed to go into the final patch series. But there
> are too many subtle changes in both HSW and LPT that are much easier to
> spot with this extra debugging when attaching a dmesg output in case of
> problems.
> 
> In other words, this is ugly, but if you run into an issue and send me
> dmesg with those included, my chances of investigating the problems will
> increase exponentially.

This should already by covered by the tracepoints. I guess you just
lacked the magic patch to enable ftrace on module load.

1289311867-10096-1-git-send-email-chris@chris-wilson.co.uk

I was hoping that since Steven Rostedt agreed and seemed to convince Rusty
as well, he would pick it up... So it could do with some love.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 23/37] drm/i915: do not set 6BPP dithering on haswell

[Eugeni Dodonov]

[-- Attachment #1.1: Type: text/plain, Size: 703 bytes --]

On Thu, Mar 22, 2012 at 07:16, Daniel Vetter <daniel@ffwll.ch> wrote:

> On Wed, Mar 21, 2012 at 10:09:58PM -0300, Eugeni Dodonov wrote:
> > We don't have those bits on Haswell anymore, so do not set them.
> >
> > Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
>
> Hm, how is 6bpp dithering supposed to work now, when e.g. a lame dp link
> can't handle more due to bandwidth issues?
>

It is handled when configuring DDI link instead now. So same functionality,
but in different place.

I also noticed that this my patch ended up in a wrong place - in
i9xx_crtc_mode_set instead of ironlake_crtc_mode_set; I'll have to rework
it anyway. Duh...

-- 
Eugeni Dodonov
<http://eugeni.dodonov.net/>

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Re: [PATCH 26/37] drm/i915: reuse Ivybridge interrupts code for Haswell

[Eugeni Dodonov]

[-- Attachment #1.1: Type: text/plain, Size: 759 bytes --]

On Thu, Mar 22, 2012 at 07:22, Daniel Vetter <daniel@ffwll.ch> wrote:

> On Wed, Mar 21, 2012 at 10:10:01PM -0300, Eugeni Dodonov wrote:
> > Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
>
> Hm, I have a feeling that some of these s/IS_IVB/IS_GEN7/ checks will
> collide with the vlv code. I guess neither Jesse nor you have tried to
> merge in each another's branch yet. This will be fun to sort out ;-)
>

Yep, we haven't tried yet :).

HSW interrupts handling seems to be very similar to IVB up to the point I
investigated, but anyway, I think most of this code will have to be adapted
between those branches. Both are Gen7, but some subtle differences make
them way to different in some places.

-- 
Eugeni Dodonov
<http://eugeni.dodonov.net/>

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Re: [PATCH 07/37] drm/i915: add DP_TP_CTL registers

[Eugeni Dodonov]

[-- Attachment #1.1: Type: text/plain, Size: 563 bytes --]

On Thu, Mar 22, 2012 at 07:43, Chris Wilson <chris@chris-wilson.co.uk>wrote:

> On Wed, 21 Mar 2012 22:09:42 -0300, Eugeni Dodonov <
> eugeni.dodonov@intel.com> wrote:
> > This is one set of those registers for each pipe.
>
Would these not benefit from a #define DP_TP_CTL(pipe)?
>

Sorry, my typo went in - there is one set of those registers for each
*port*. I defined DP_TP_CTL(pipe) for this (and all other DP_TP_* ones),
but in the end I figured out that pipes need to be programmed independently
from ports.

-- 
Eugeni Dodonov
<http://eugeni.dodonov.net/>

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Re: [PATCH 07/37] drm/i915: add DP_TP_CTL registers

[Daniel Vetter]

On Thu, Mar 22, 2012 at 09:18:32AM -0300, Eugeni Dodonov wrote:
> On Thu, Mar 22, 2012 at 07:43, Chris Wilson <chris@chris-wilson.co.uk>wrote:
> 
> > On Wed, 21 Mar 2012 22:09:42 -0300, Eugeni Dodonov <
> > eugeni.dodonov@intel.com> wrote:
> > > This is one set of those registers for each pipe.
> >
> Would these not benefit from a #define DP_TP_CTL(pipe)?
> >
> 
> Sorry, my typo went in - there is one set of those registers for each
> *port*. I defined DP_TP_CTL(pipe) for this (and all other DP_TP_* ones),
> but in the end I figured out that pipes need to be programmed independently
> from ports.

Hm, so maybe it's time to add an enum ports as Chris suggested? Or is that
stuff to different on the different platforms to make sense?
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 05/37] drm/i915: add support for power wells

[Rodrigo Vivi]

Like in this patch, the defines indentation in some patches in this
series sounds strange, wrong, or at least different from the one
already in use.

So, since I don't know if we should care about indentation now, for
those patches I'll just mark like this:

* indentation
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
<eugeni.dodonov@intel.com> wrote:
> This defines the registers used by different power wells.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |   13 +++++++++++++
>  1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 52a06be..ddc9c87 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3850,4 +3850,17 @@
>  #define   AUD_CONFIG_PIXEL_CLOCK_HDMI          (0xf << 16)
>  #define   AUD_CONFIG_DISABLE_NCTS              (1 << 3)
>
> +/* HSW Power Wells */
> +#define HSW_PWR_WELL_CTL1              0x45400         /* BIOS */
> +#define HSW_PWR_WELL_CTL2              0x45404         /* Driver */
> +#define HSW_PWR_WELL_CTL3              0x45408         /* KVMR */
> +#define HSW_PWR_WELL_CTL4              0x4540C         /* Debug */
> +#define   HSW_PWR_WELL_ENABLE  (1<<31)
> +#define   HSW_PWR_WELL_STATE   (1<<30)
> +#define HSW_PWR_WELL_CTL5              0x45410
> +#define   HSW_PWR_WELL_ENABLE_SINGLE_STEP      (1<<31)
> +#define   HSW_PWR_WELL_PWR_GATE_OVERRIDE       (1<<20)
> +#define   HSW_PWR_WELL_FORCE_ON        (1<<19)
> +#define HSW_PWR_WELL_CTL6              0x45414
> +
>  #endif /* _I915_REG_H_ */
> --
> 1.7.9.2
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net

Re: [PATCH 06/37] drm/i915: add DDI registers

[Rodrigo Vivi]

*indentation
and it is missing
#define  PIPE_DDI_MODE_SELECT_DP_MST  (3<<24)

Otherwise:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
<eugeni.dodonov@intel.com> wrote:
> There is one set of such registers for each pipe (A/B/C/EDP).
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |   27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ddc9c87..09b2267 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3863,4 +3863,31 @@
>  #define   HSW_PWR_WELL_FORCE_ON        (1<<19)
>  #define HSW_PWR_WELL_CTL6              0x45414
>
> +/* Per-pipe DDI Function Control */
> +#define PIPE_DDI_FUNC_CTL_A                    0x60400
> +#define PIPE_DDI_FUNC_CTL_B                    0x61400
> +#define PIPE_DDI_FUNC_CTL_C                    0x62400
> +#define PIPE_DDI_FUNC_CTL_EDP          0x6F400
> +#define DDI_FUNC_CTL(pipe) _PIPE(pipe, \
> +                                       PIPE_DDI_FUNC_CTL_A, \
> +                                       PIPE_DDI_FUNC_CTL_B)
> +#define  PIPE_DDI_FUNC_ENABLE          (1<<31)
> +/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
> +#define  PIPE_DDI_SELECT_DDI_B (0x1<<28)
> +#define  PIPE_DDI_SELECT_DDI_C (0x2<<28)
> +#define  PIPE_DDI_SELECT_DDI_D (0x3<<28)
> +#define  PIPE_DDI_SELECT_DDI_E (0x4<<28)
> +#define  PIPE_DDI_MODE_SELECT_HDMI     (0<<24)
> +#define  PIPE_DDI_MODE_SELECT_DVI      (1<<24)
> +#define  PIPE_DDI_MODE_SELECT_DP_SST   (2<<24)
> +#define  PIPE_DDI_MODE_SELECT_FDI      (4<<24)
> +#define  PIPE_DDI_BPC_8                                (0<<20)
> +#define  PIPE_DDI_BPC_10                       (1<<20)
> +#define  PIPE_DDI_BPC_6                                (2<<20)
> +#define  PIPE_DDI_BPC_12                       (3<<20)
> +#define  PIPE_DDI_BFI_ENABLE           (1<<4)
> +#define  PIPE_DDI_PORT_WIDTH_X1                        (0<<1)
> +#define  PIPE_DDI_PORT_WIDTH_X2                        (1<<1)
> +#define  PIPE_DDI_PORT_WIDTH_X4                        (3<<1)
> +
>  #endif /* _I915_REG_H_ */
> --
> 1.7.9.2
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



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Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net

Re: [PATCH 09/37] drm/i915: add definitions for DDI_BUF_CTL registers

[Rodrigo Vivi]

* indentation
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
<eugeni.dodonov@intel.com> wrote:
> There is one instance of those registers for each DDI port.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |   23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 3831fe7..2927460 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3914,4 +3914,27 @@
>  #define DP_TP_STATUS_E                 0x64444
>  #define  DP_TP_STATUS_AUTOTRAIN_DONE   (1<<12)
>
> +/* DDI Buffer Control */
> +#define DDI_BUF_CTL_A                          0x64000
> +#define DDI_BUF_CTL_B                          0x64100
> +#define DDI_BUF_CTL_C                          0x64200
> +#define DDI_BUF_CTL_D                          0x64300
> +#define DDI_BUF_CTL_E                          0x64400
> +#define  DDI_BUF_CTL_ENABLE                    (1<<31)
> +#define  DDI_BUF_EMP_400MV_0DB_HSW             (0<<24)   /* Sel0 */
> +#define  DDI_BUF_EMP_400MV_3_5DB_HSW   (1<<24)   /* Sel1 */
> +#define  DDI_BUF_EMP_400MV_6DB_HSW             (2<<24)   /* Sel2 */
> +#define  DDI_BUF_EMP_400MV_9_5DB_HSW   (3<<24)   /* Sel3 */
> +#define  DDI_BUF_EMP_600MV_0DB_HSW             (4<<24)   /* Sel4 */
> +#define  DDI_BUF_EMP_600MV_3_5DB_HSW   (5<<24)   /* Sel5 */
> +#define  DDI_BUF_EMP_600MV_6DB_HSW             (6<<24)   /* Sel6 */
> +#define  DDI_BUF_EMP_800MV_0DB_HSW             (7<<24)   /* Sel7 */
> +#define  DDI_BUF_EMP_800MV_3_5DB_HSW   (8<<24)   /* Sel8 */
> +#define  DDI_BUF_EMP_MASK                              (0xf<<24)
> +#define  DDI_BUF_IS_IDLE                               (1<<7)
> +#define  DDI_PORT_WIDTH_X1                             (0<<1)
> +#define  DDI_PORT_WIDTH_X2                             (1<<1)
> +#define  DDI_PORT_WIDTH_X4                             (3<<1)
> +#define  DDI_INIT_DISPLAY_DETECTED             (1<<0)
> +
>  #endif /* _I915_REG_H_ */
> --
> 1.7.9.2
>
> _______________________________________________
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GPG: 0x905BE242 @ wwwkeys.pgp.net

Re: [PATCH 14/37] drm/i915: add PIXCLK_GATE register

[Rodrigo Vivi]

* indentation
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
<eugeni.dodonov@intel.com> wrote:
> Pixel clock gating control for Lynx point.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |    6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4ee8965..9ff9856 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3957,4 +3957,10 @@
>  #define  SBI_CTL_OP_CRWR               (0x7<<8)
>  #define  SBI_RESPONSE                  (0x1<<1)
>  #define  SBI_READY                             (0x1<<0)
> +
> +/* LPT PIXCLK_GATE */
> +#define PIXCLK_GATE                            0xC6020
> +#define  PIXCLK_GATE_UNGATE            1<<0
> +#define  PIXCLK_GATE_GATE              0<<0
> +
>  #endif /* _I915_REG_H_ */
> --
> 1.7.9.2
>
> _______________________________________________
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-- 
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Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net

Re: [PATCH 16/37] drm/i915: add port clock selection support for HSW

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
<eugeni.dodonov@intel.com> wrote:
> Multiple clocks can drive different outputs.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |   23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e38dafc..eebe9d3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3971,4 +3971,27 @@
>  #define  SPLL_PLL_FREQ_810MHz  (0<<26)
>  #define  SPLL_PLL_FREQ_1350MHz (1<<26)
>
> +/* Port clock selection */
> +#define PORT_CLK_SEL_A                 0x46100
> +#define PORT_CLK_SEL_B                 0x46104
> +#define PORT_CLK_SEL_C                 0x46108
> +#define PORT_CLK_SEL_D                 0x4610C
> +#define PORT_CLK_SEL_E                 0x46110
> +#define  PORT_CLK_SEL_LCPLL_2700       (0<<29)
> +#define  PORT_CLK_SEL_LCPLL_1350       (1<<29)
> +#define  PORT_CLK_SEL_LCPLL_810                (2<<29)
> +#define  PORT_CLK_SEL_SPLL                     (3<<29)
> +#define  PORT_CLK_SEL_WRPLL1           (4<<29)
> +#define  PORT_CLK_SEL_WRPLL2           (5<<29)
> +
> +/* Pipe clock selection */
> +#define PIPE_CLK_SEL_A                 0x46140
> +#define PIPE_CLK_SEL_B                 0x46144
> +#define PIPE_CLK_SEL(pipe) _PIPE(pipe, \
> +                                       PIPE_CLK_SEL_A, \
> +                                       PIPE_CLK_SEL_B)
> +#define  PIPE_CLK_SEL_DDIB             (2<<29)
> +#define  PIPE_CLK_SEL_DDIC             (3<<29)
> +#define  PIPE_CLK_SEL_DDID             (4<<29)
> +#define  PIPE_CLK_SEL_DDIE             (5<<29)
>  #endif /* _I915_REG_H_ */
> --
> 1.7.9.2
>
> _______________________________________________
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Re: [PATCH 12/37] drm/i915: add SBI registers

[Rodrigo Vivi]

* indentation
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
<eugeni.dodonov@intel.com> wrote:
> Those are responsible for the Sideband Interface programming.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |   10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0af47b4..4ee8965 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3947,4 +3947,14 @@
>  #define DDI_BUF_TRANS_D                                0x64F20
>  #define DDI_BUF_TRANS_E                                0x64F80
>
> +/* Sideband Interface (SBI) is programmed indirectly, via
> + * SBI_ADDR, which contains the register offset; and SBI_DATA,
> + * which contains the payload */
> +#define SBI_ADDR                               0xC6000
> +#define SBI_DATA                               0xC6004
> +#define SBI_CTL_STAT                   0xC6008
> +#define  SBI_CTL_OP_CRRD               (0x6<<8)
> +#define  SBI_CTL_OP_CRWR               (0x7<<8)
> +#define  SBI_RESPONSE                  (0x1<<1)
> +#define  SBI_READY                             (0x1<<0)
>  #endif /* _I915_REG_H_ */
> --
> 1.7.9.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net

Re: [PATCH 17/37] drm/i915: add SSC offsets for SBI access

[Rodrigo Vivi]

* indentation
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
<eugeni.dodonov@intel.com> wrote:
> Different registers are identified by their target id and offset. To
> simplify their programming, they are called as <RegisterName><TargetId>.
> For example, SSCCTL register accessed through SBI at target id 6 and
> offset 0c is called SBI_SSCCTL6.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |   15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index eebe9d3..193fb11 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3958,6 +3958,21 @@
>  #define  SBI_RESPONSE                  (0x1<<1)
>  #define  SBI_READY                             (0x1<<0)
>
> +/* SBI offsets */
> +#define  SBI_SSCDIVINTPHASE6           0x0600
> +#define   SBI_SSCDIVINTPHASE_DIVSEL_MASK       ((0x7f)<<1)
> +#define   SBI_SSCDIVINTPHASE_DIVSEL(x)         ((x)<<1)
> +#define   SBI_SSCDIVINTPHASE_INCVAL_MASK       ((0x7f)<<8)
> +#define   SBI_SSCDIVINTPHASE_INCVAL(x)         ((x)<<8)
> +#define   SBI_SSCDIVINTPHASE_DIR(x)                    ((x)<<15)
> +#define   SBI_SSCDIVINTPHASE_PROPAGATE         (1<<0)
> +#define  SBI_SSCCTL                                    0x020c
> +#define  SBI_SSCCTL6                           0x060C
> +#define   SBI_SSCCTL_DISABLE           (1<<0)
> +#define  SBI_SSCAUXDIV6                                0x0610
> +#define   SBI_SSCAUXDIV_FINALDIV2SEL(x)                ((x)<<4)
> +#define  SBI_DBUFF0                                    0x2a00
> +
>  /* LPT PIXCLK_GATE */
>  #define PIXCLK_GATE                            0xC6020
>  #define  PIXCLK_GATE_UNGATE            1<<0
> --
> 1.7.9.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net

Re: [PATCH 20/37] drm/i915: add WM_LINETIME registers

[Rodrigo Vivi]

* indentation
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
<eugeni.dodonov@intel.com> wrote:
> Watermark line time registers for display low power watermark.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |   10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fa9e3a8..76f7acb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4021,4 +4021,14 @@
>  #define  LCPLL_CD_CLOCK_DISABLE        (1<<25)
>  #define  LCPLL_CD2X_CLOCK_DISABLE      (1<<23)
>
> +/* Pipe WM_LINETIME - watermark line time */
> +#define PIPE_WM_LINETIME_A             0x45270
> +#define PIPE_WM_LINETIME_B             0x45274
> +#define PIPE_WM_LINETIME(pipe) _PIPE(pipe, \
> +                                       PIPE_WM_LINETIME_A, \
> +                                       PIPE_WM_LINETIME_A)
> +#define   PIPE_WM_LINETIME_LINETIME_MASK               (0x1ff)
> +#define   PIPE_WM_LINETIME_LINETIME(x)                 ((x))
> +#define   PIPE_WM_LINETIME_IPS_LINETIME_MASK   (0x1ff<<16)
> +#define   PIPE_WM_LINETIME_IPS_LINETIME(x)             ((x)<<16)
>  #endif /* _I915_REG_H_ */
> --
> 1.7.9.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net

Re: [PATCH 15/37] drm/i915: add S PLL control

[Rodrigo Vivi]

* indentation
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
<eugeni.dodonov@intel.com> wrote:
> This PLL control can drive DDI ports at desired frequencies for
> DisplayPort and FDI connections.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |    8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9ff9856..e38dafc 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3963,4 +3963,12 @@
>  #define  PIXCLK_GATE_UNGATE            1<<0
>  #define  PIXCLK_GATE_GATE              0<<0
>
> +/* SPLL */
> +#define SPLL_CTL                               0x46020
> +#define  SPLL_PLL_ENABLE               (1<<31)
> +#define  SPLL_PLL_SCC                  (1<<28)
> +#define  SPLL_PLL_NON_SCC              (2<<28)
> +#define  SPLL_PLL_FREQ_810MHz  (0<<26)
> +#define  SPLL_PLL_FREQ_1350MHz (1<<26)
> +
>  #endif /* _I915_REG_H_ */
> --
> 1.7.9.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net

Re: [PATCH 19/37] drm/i915: add LCPLL control registers

[Rodrigo Vivi]

 LCPLL_PLL_ENABLE should be  (0<<31)\

Otherwise

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
<eugeni.dodonov@intel.com> wrote:
> Those are used to control the display core clock.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |    7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 03fb10d..fa9e3a8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4014,4 +4014,11 @@
>  #define GTCCLK_EN                              0xC6030
>  #define  GTCCLK_EN_ENABLE              (1<<0)
>
> +/* LCPLL Control */
> +#define LCPLL_CTL                              0x130040
> +#define  LCPLL_PLL_ENABLE              (1<<31)
> +#define  LCPLL_PLL_LOCK                        (1<<30)
> +#define  LCPLL_CD_CLOCK_DISABLE        (1<<25)
> +#define  LCPLL_CD2X_CLOCK_DISABLE      (1<<23)
> +
>  #endif /* _I915_REG_H_ */
> --
> 1.7.9.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net

Re: [PATCH 18/37] drm/i915: add GTC registers

[Rodrigo Vivi]

* indentation
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
<eugeni.dodonov@intel.com> wrote:
> Add Global Time Clock registers
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |    5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 193fb11..03fb10d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4009,4 +4009,9 @@
>  #define  PIPE_CLK_SEL_DDIC             (3<<29)
>  #define  PIPE_CLK_SEL_DDID             (4<<29)
>  #define  PIPE_CLK_SEL_DDIE             (5<<29)
> +
> +/* Global time clock */
> +#define GTCCLK_EN                              0xC6030
> +#define  GTCCLK_EN_ENABLE              (1<<0)
> +
>  #endif /* _I915_REG_H_ */
> --
> 1.7.9.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net

Re: [PATCH 11/37] drm/i915: add definition of DDI buffer translations regs

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
<eugeni.dodonov@intel.com> wrote:
> Those registers are used to train DDI buffer translations for each link
> type.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |    7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b732aa1..0af47b4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3940,4 +3940,11 @@
>  #define  DDI_PORT_WIDTH_X4                             (3<<1)
>  #define  DDI_INIT_DISPLAY_DETECTED             (1<<0)
>
> +/* DDI Buffer Translations */
> +#define DDI_BUF_TRANS_A                                0x64E00
> +#define DDI_BUF_TRANS_B                                0x64E60
> +#define DDI_BUF_TRANS_C                                0x64EC0
> +#define DDI_BUF_TRANS_D                                0x64F20
> +#define DDI_BUF_TRANS_E                                0x64F80
> +
>  #endif /* _I915_REG_H_ */
> --
> 1.7.9.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net

Re: [PATCH 19/37] drm/i915: add LCPLL control registers

[Daniel Vetter]

On Mon, Mar 26, 2012 at 02:42:30PM -0300, Rodrigo Vivi wrote:
>  LCPLL_PLL_ENABLE should be  (0<<31)\

I that case I think we should name it LCPLL_PLL_DISABLE (and use (1<<31)
obviously).
-Daniel

> 
> Otherwise
> 
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
> 
> On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
> <eugeni.dodonov@intel.com> wrote:
> > Those are used to control the display core clock.
> >
> > Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h |    7 +++++++
> >  1 file changed, 7 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 03fb10d..fa9e3a8 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4014,4 +4014,11 @@
> >  #define GTCCLK_EN                              0xC6030
> >  #define  GTCCLK_EN_ENABLE              (1<<0)
> >
> > +/* LCPLL Control */
> > +#define LCPLL_CTL                              0x130040
> > +#define  LCPLL_PLL_ENABLE              (1<<31)
> > +#define  LCPLL_PLL_LOCK                        (1<<30)
> > +#define  LCPLL_CD_CLOCK_DISABLE        (1<<25)
> > +#define  LCPLL_CD2X_CLOCK_DISABLE      (1<<23)
> > +
> >  #endif /* _I915_REG_H_ */
> > --
> > 1.7.9.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br
> GPG: 0x905BE242 @ wwwkeys.pgp.net
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 12/37] drm/i915: add SBI registers

[Rodrigo Vivi]

Ops, actually I'm in doubt about this one, for me:

SBI_RESPONSE  should be  (0x0<<1)
SBI_READY  should be    (0x0<<0)

let's double check this togheter, otherwise:

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Mon, Mar 26, 2012 at 2:40 PM, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
> * indentation
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
>
> On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
> <eugeni.dodonov@intel.com> wrote:
>> Those are responsible for the Sideband Interface programming.
>>
>> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h |   10 ++++++++++
>>  1 file changed, 10 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 0af47b4..4ee8965 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -3947,4 +3947,14 @@
>>  #define DDI_BUF_TRANS_D                                0x64F20
>>  #define DDI_BUF_TRANS_E                                0x64F80
>>
>> +/* Sideband Interface (SBI) is programmed indirectly, via
>> + * SBI_ADDR, which contains the register offset; and SBI_DATA,
>> + * which contains the payload */
>> +#define SBI_ADDR                               0xC6000
>> +#define SBI_DATA                               0xC6004
>> +#define SBI_CTL_STAT                   0xC6008
>> +#define  SBI_CTL_OP_CRRD               (0x6<<8)
>> +#define  SBI_CTL_OP_CRWR               (0x7<<8)
>> +#define  SBI_RESPONSE                  (0x1<<1)
>> +#define  SBI_READY                             (0x1<<0)
>>  #endif /* _I915_REG_H_ */
>> --
>> 1.7.9.2
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br
> GPG: 0x905BE242 @ wwwkeys.pgp.net



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net

Re: [PATCH 36/37] drm/i915: add warning when using old bits on Haswell/LPT

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Mar 21, 2012 at 10:10 PM, Eugeni Dodonov
<eugeni.dodonov@intel.com> wrote:
> Those have different functionality on Haswell architecture, so let's
> trigger a warning message when we are going through a path we should not
> go into on Haswell.
>
> This patch is here for make debugging and log tracing easier, it should
> go away in the future, we we'll stop hitting those code paths.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |   59 +++++++++++++++++++++++++++-------
>  1 file changed, 47 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a37e0b7..10b92e8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -847,9 +847,16 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv,
>        u32 val;
>        bool cur_state;
>
> -       reg = FDI_TX_CTL(pipe);
> -       val = I915_READ(reg);
> -       cur_state = !!(val & FDI_TX_ENABLE);
> +       if (IS_HASWELL(dev_priv->dev)) {
> +               DRM_ERROR("Attempting to check FDI_TX_CTL on Haswell, using DDI instead\n");
> +               reg = DDI_FUNC_CTL(pipe);
> +               val = I915_READ(reg);
> +               cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
> +       } else {
> +               reg = FDI_TX_CTL(pipe);
> +               val = I915_READ(reg);
> +               cur_state = !!(val & FDI_TX_ENABLE);
> +       }
>        WARN(cur_state != state,
>             "FDI TX state assertion failure (expected %s, current %s)\n",
>             state_string(state), state_string(cur_state));
> @@ -864,9 +871,14 @@ static void assert_fdi_rx(struct drm_i915_private *dev_priv,
>        u32 val;
>        bool cur_state;
>
> -       reg = FDI_RX_CTL(pipe);
> -       val = I915_READ(reg);
> -       cur_state = !!(val & FDI_RX_ENABLE);
> +       if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
> +                       DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
> +                       return;
> +       } else {
> +               reg = FDI_RX_CTL(pipe);
> +               val = I915_READ(reg);
> +               cur_state = !!(val & FDI_RX_ENABLE);
> +       }
>        WARN(cur_state != state,
>             "FDI RX state assertion failure (expected %s, current %s)\n",
>             state_string(state), state_string(cur_state));
> @@ -884,6 +896,11 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
>        if (dev_priv->info->gen == 5)
>                return;
>
> +       if (IS_HASWELL(dev_priv->dev)) {
> +               DRM_ERROR("Attempting to check FDI_TX_PLL on Haswell, aborting\n");
> +               return;
> +       }
> +
>        reg = FDI_TX_CTL(pipe);
>        val = I915_READ(reg);
>        WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
> @@ -895,6 +912,10 @@ static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
>        int reg;
>        u32 val;
>
> +       if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
> +               DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
> +               return;
> +       }
>        reg = FDI_RX_CTL(pipe);
>        val = I915_READ(reg);
>        WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
> @@ -1000,6 +1021,11 @@ static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
>        u32 val;
>        bool enabled;
>
> +       if (HAS_PCH_LPT(dev_priv->dev)) {
> +               DRM_ERROR("LPT does not has PCH refclk, skipping check\n");
> +               return;
> +       }
> +
>        val = I915_READ(PCH_DREF_CONTROL);
>        enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
>                            DREF_SUPERSPREAD_SOURCE_MASK));
> @@ -1323,6 +1349,10 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
>        assert_fdi_tx_enabled(dev_priv, pipe);
>        assert_fdi_rx_enabled(dev_priv, pipe);
>
> +       if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
> +               DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
> +               return;
> +       }
>        reg = TRANSCONF(pipe);
>        val = I915_READ(reg);
>        pipeconf_val = I915_READ(PIPECONF(pipe));
> @@ -3308,13 +3338,18 @@ static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
>        udelay(200);
>
>        /* Enable CPU FDI TX PLL, always on for Ironlake */
> -       reg = FDI_TX_CTL(pipe);
> -       temp = I915_READ(reg);
> -       if ((temp & FDI_TX_PLL_ENABLE) == 0) {
> -               I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
> +       if (IS_HASWELL(dev)) {
> +               DRM_ERROR("Skipping enablement of FDI_TX_PLL on Haswell\n");
> +               return;
> +       } else {
> +               reg = FDI_TX_CTL(pipe);
> +               temp = I915_READ(reg);
> +               if ((temp & FDI_TX_PLL_ENABLE) == 0) {
> +                       I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
>
> -               POSTING_READ(reg);
> -               udelay(100);
> +                       POSTING_READ(reg);
> +                       udelay(100);
> +               }
>        }
>  }
>
> --
> 1.7.9.2
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net

Re: [PATCH 32/37] drm/i915: perform Haswell DDI link training in FDI mode

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Mar 21, 2012 at 10:10 PM, Eugeni Dodonov
<eugeni.dodonov@intel.com> wrote:
> This patch attempts at following the modeset sequence closely, retrying
> with different voltages if the DP_TP_STATUS reports a failed training.
>
> For training, we add a table of recommended settings for FDI, HDMI and DP
> connections. For FDI and DP modes, we also add the HDMI buffer
> translation as the last item. Those are ignored in such modes, so there is
> no harm in having them set.
>
> Initially, we use DDI E for FDI connectivity.  This is the suggested
> configuration, and this seems to be what should work the best with FDI.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |  170 ++++++++++++++++++++++++++++++++++
>  1 file changed, 170 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index b1ad10a..04625d5 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1409,6 +1409,16 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
>                /* FIXME: assert CPU port conditions for SNB+ */
>        }
>
> +       /* On HSW, enable PIPE_DDI_FUNC_CTL for the pipe */
> +       if (IS_HASWELL(dev_priv->dev)) {
> +               I915_WRITE(DDI_FUNC_CTL(pipe),
> +                               I915_READ(DDI_FUNC_CTL(pipe)) |
> +                                       PIPE_DDI_SELECT_DDI_E |
> +                                       PIPE_DDI_PORT_WIDTH_X2 |
> +                                       PIPE_DDI_MODE_SELECT_FDI |
> +                                       PIPE_DDI_FUNC_ENABLE);
> +       }
> +
>        reg = PIPECONF(pipe);
>        val = I915_READ(reg);
>        if (val & PIPECONF_ENABLE)
> @@ -2698,6 +2708,151 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
>        DRM_DEBUG_KMS("FDI train done.\n");
>  }
>
> +static const long hsw_ddi_translations_dp[] = {
> +       0x00FFFFFF, 0x0006000E,
> +       0x00D75FFF, 0x0005000A,
> +       0x00C30FFF, 0x00040006,
> +       0x80AAAFFF, 0x000B0000,
> +       0x00FFFFFF, 0x0005000A,
> +       0x00D75FFF, 0x000C0004,
> +       0x80C30FFF, 0x000B0000,
> +       0x00FFFFFF, 0x00040006,
> +       0x80D75FFF, 0x000B0000,
> +       0x00FFFFFF, 0x00040006
> +};
> +
> +static const long hsw_ddi_translations_fdi[] = {
> +       0x00FFFFFF, 0x0007000E,
> +       0x00D75FFF, 0x000F000A,
> +       0x00C30FFF, 0x00060006,
> +       0x00AAAFFF, 0x001E0000,
> +       0x00FFFFFF, 0x000F000A,
> +       0x00D75FFF, 0x00160004,
> +       0x00C30FFF, 0x001E0000,
> +       0x00FFFFFF, 0x00060006,
> +       0x00D75FFF, 0x001E0000,
> +       0x00FFFFFF, 0x00040006
> +};
> +
> +/* For HDMI, we are only interested in the last entry */
> +static const long hsw_ddi_translations_hdmi[] = {
> +       0x0, 0x0,
> +       0x0, 0x0,
> +       0x0, 0x0,
> +       0x0, 0x0,
> +       0x0, 0x0,
> +       0x0, 0x0,
> +       0x0, 0x0,
> +       0x0, 0x0,
> +       0x0, 0x0,
> +       0x00FFFFFF, 0x00040006
> +};
> +
> +
> +static const long hsw_ddi_buf_ctl_values[] = {
> +       DDI_BUF_EMP_400MV_0DB_HSW,
> +       DDI_BUF_EMP_400MV_3_5DB_HSW,
> +       DDI_BUF_EMP_400MV_6DB_HSW,
> +       DDI_BUF_EMP_400MV_9_5DB_HSW,
> +       DDI_BUF_EMP_600MV_0DB_HSW,
> +       DDI_BUF_EMP_600MV_3_5DB_HSW,
> +       DDI_BUF_EMP_600MV_6DB_HSW,
> +       DDI_BUF_EMP_800MV_0DB_HSW,
> +       DDI_BUF_EMP_800MV_3_5DB_HSW
> +};
> +
> +
> +/* Link training for HSW parts */
> +static void hsw_fdi_link_train(struct drm_crtc *crtc)
> +{
> +       struct drm_device *dev = crtc->dev;
> +       struct drm_i915_private *dev_priv = dev->dev_private;
> +       struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +       int pipe = intel_crtc->pipe;
> +       u32 reg, temp, i;
> +
> +       /* Prior to enabling DDI, configure buffer translation with FDI values */
> +       for (i=0, reg=DDI_BUF_TRANS_E; i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
> +               I915_WRITE(reg, hsw_ddi_translations_fdi[i]);
> +               reg += 4;
> +       }
> +
> +       /* Configure CPU PLL, wait for warmup */
> +       I915_WRITE(SPLL_CTL,
> +                       SPLL_PLL_ENABLE |
> +                       SPLL_PLL_FREQ_1350MHz |
> +                       SPLL_PLL_SCC);
> +
> +       /* Use SPLL to drive the output when in FDI mode */
> +       I915_WRITE(PORT_CLK_SEL_E,
> +                       PORT_CLK_SEL_SPLL);
> +       I915_WRITE(PIPE_CLK_SEL(pipe),
> +                       PIPE_CLK_SEL_DDIE);
> +
> +       udelay(20);
> +
> +       /* Start the training iterating through available voltages and emphasis */
> +       for (i=0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values); i++) {
> +               /* Configure DP_TP_CTL with auto-training */
> +               I915_WRITE(DP_TP_CTL_E,
> +                                       DP_TP_CTL_FDI_AUTOTRAIN |
> +                                       DP_TP_CTL_ENHANCED_FRAME_ENABLE |
> +                                       DP_TP_CTL_LINK_TRAIN_PAT1 |
> +                                       DP_TP_CTL_ENABLE);
> +
> +               /* Configure and enable DDI_BUF_CTL for DDI E with next voltage */
> +               temp = I915_READ(DDI_BUF_CTL_E);
> +               temp = (temp & ~DDI_BUF_EMP_MASK);
> +               I915_WRITE(DDI_BUF_CTL_E,
> +                               temp |
> +                               DDI_BUF_CTL_ENABLE |
> +                               DDI_PORT_WIDTH_X2 |
> +                               hsw_ddi_buf_ctl_values[i]);
> +
> +               udelay(600);
> +
> +               /* Enable CPU FDI Receiver with auto-training */
> +               I915_WRITE(FDI_RX_CTL(pipe),
> +                               I915_READ(FDI_RX_CTL(pipe)) |
> +                                       FDI_LINK_TRAIN_AUTO |
> +                                       FDI_RX_ENABLE |
> +                                       FDI_LINK_TRAIN_PATTERN_1_CPT |
> +                                       FDI_RX_ENHANCE_FRAME_ENABLE |
> +                                       LPT_FDI_PORT_WIDTH_2X |
> +                                       FDI_RX_PLL_ENABLE);
> +               POSTING_READ(reg);
> +               udelay(100);
> +
> +               temp = I915_READ(DP_TP_STATUS_E);
> +               if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
> +                       DRM_INFO("BUF_CTL training done on %d step\n", i);
> +
> +                       /* Enable normal pixel sending for FDI */
> +                       I915_WRITE(DP_TP_CTL_E,
> +                                               DP_TP_CTL_FDI_AUTOTRAIN |
> +                                               DP_TP_CTL_LINK_TRAIN_NORMAL |
> +                                               DP_TP_CTL_ENHANCED_FRAME_ENABLE |
> +                                               DP_TP_CTL_ENABLE);
> +
> +                       break;
> +               } else {
> +                       DRM_ERROR("Error training BUF_CTL %d\n", i);
> +
> +                       /* Disable DP_TP_CTL and FDI_RX_CTL) and retry */
> +                       I915_WRITE(DP_TP_CTL_E,
> +                                       I915_READ(DP_TP_CTL_E) &
> +                                               ~DP_TP_CTL_ENABLE);
> +                       I915_WRITE(FDI_RX_CTL(pipe),
> +                                       I915_READ(FDI_RX_CTL(pipe)) &
> +                                               ~FDI_RX_PLL_ENABLE);
> +                       continue;
> +               }
> +       }
> +
> +
> +       DRM_DEBUG_KMS("FDI train done.\n");
> +}
> +
>  /* Manual link training for Ivy Bridge A0 parts */
>  static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
>  {
> @@ -3019,6 +3174,10 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>                        temp |= (TRANSC_DPLL_ENABLE | transc_sel);
>                }
>                I915_WRITE(PCH_DPLL_SEL, temp);
> +       } else if (HAS_PCH_LPT(dev)) {
> +               /* DDIE clock is recommented for FDI connections */
> +               I915_WRITE(PIPE_CLK_SEL(pipe),
> +                               PIPE_CLK_SEL_DDIE);
>        }
>
>        /* set transcoder timing, panel must allow it */
> @@ -8975,6 +9134,17 @@ static void intel_init_display(struct drm_device *dev)
>                        }
>                        dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
>                        dev_priv->display.write_eld = ironlake_write_eld;
> +               } else if (IS_HASWELL(dev)) {
> +                       dev_priv->display.fdi_link_train = hsw_fdi_link_train;
> +                       if (SNB_READ_WM0_LATENCY()) {
> +                               dev_priv->display.update_wm = sandybridge_update_wm;
> +                       } else {
> +                               DRM_DEBUG_KMS("Failed to read display plane latency. "
> +                                             "Disable CxSR\n");
> +                               dev_priv->display.update_wm = NULL;
> +                       }
> +                       dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
> +                       dev_priv->display.write_eld = ironlake_write_eld;
>                } else
>                        dev_priv->display.update_wm = NULL;
>        } else if (IS_PINEVIEW(dev)) {
> --
> 1.7.9.2
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net

Re: [PATCH 34/37] drm/i915: do not use fdi_normal_train on haswell

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Mar 21, 2012 at 10:10 PM, Eugeni Dodonov
<eugeni.dodonov@intel.com> wrote:
> This should be already configured when FDI auto-negotiation is done.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |    3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 8a839be..5f6cb35 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3195,7 +3195,8 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>        I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
>        I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
>
> -       intel_fdi_normal_train(crtc);
> +       if (!IS_HASWELL(dev))
> +               intel_fdi_normal_train(crtc);
>
>        /* For PCH DP, enable TRANS_DP_CTL */
>        if (HAS_PCH_CPT(dev) &&
> --
> 1.7.9.2
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net

Re: [PATCH 27/37] drm/i915: share pipe count handling with Ivybridge

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Mar 21, 2012 at 10:10 PM, Eugeni Dodonov
<eugeni.dodonov@intel.com> wrote:
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 27ab70d..2978597 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2308,7 +2308,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
>        case 1:
>                break;
>        case 2:
> -               if (IS_IVYBRIDGE(dev))
> +               if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
>                        break;
>                /* fall through otherwise */
>        default:
> --
> 1.7.9.2
>
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-- 
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Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net

Re: [PATCH 25/37] drm/i915: haswell has 3 pipes as well

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Mar 21, 2012 at 10:10 PM, Eugeni Dodonov
<eugeni.dodonov@intel.com> wrote:
> They work differently, but the count is the same.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_dma.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 9341eb8..a2c0e75 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -2073,7 +2073,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
>        spin_lock_init(&dev_priv->error_lock);
>        spin_lock_init(&dev_priv->rps_lock);
>
> -       if (IS_IVYBRIDGE(dev))
> +       if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
>                dev_priv->num_pipe = 3;
>        else if (IS_MOBILE(dev) || !IS_GEN2(dev))
>                dev_priv->num_pipe = 2;
> --
> 1.7.9.2
>
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-- 
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Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net

Re: [PATCH 33/37] drm/i915: double-write DDI translation table

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Mar 21, 2012 at 10:10 PM, Eugeni Dodonov
<eugeni.dodonov@intel.com> wrote:
> Some double-buffered registers need to be written twice.
>
> Note that it is being sent as a separate patch because sometimes these
> registers do work when written only once. But double-writing on my machine
> ensured that they work more often.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |   12 ++++++++----
>  1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 04625d5..8a839be 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2769,12 +2769,16 @@ static void hsw_fdi_link_train(struct drm_crtc *crtc)
>        struct drm_i915_private *dev_priv = dev->dev_private;
>        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>        int pipe = intel_crtc->pipe;
> -       u32 reg, temp, i;
> +       u32 reg, temp, i, j;
>
>        /* Prior to enabling DDI, configure buffer translation with FDI values */
> -       for (i=0, reg=DDI_BUF_TRANS_E; i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
> -               I915_WRITE(reg, hsw_ddi_translations_fdi[i]);
> -               reg += 4;
> +       /* Those registers seem to be double-buffered - at least, the hw team writes them twice. */
> +       for (j=0; j < 2; j++) {
> +               for (i=0, reg=DDI_BUF_TRANS_E; i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
> +                       I915_WRITE(reg, hsw_ddi_translations_fdi[i]);
> +                       reg += 4;
> +               }
> +               udelay(20);
>        }
>
>        /* Configure CPU PLL, wait for warmup */
> --
> 1.7.9.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net

Re: [PATCH 28/37] drm/i915: share IVB cursor routine with Haswell

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Mar 21, 2012 at 10:10 PM, Eugeni Dodonov
<eugeni.dodonov@intel.com> wrote:
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2978597..3b3dc15 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6467,7 +6467,7 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
>        if (!visible && !intel_crtc->cursor_visible)
>                return;
>
> -       if (IS_IVYBRIDGE(dev)) {
> +       if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
>                I915_WRITE(CURPOS_IVB(pipe), pos);
>                ivb_update_cursor(crtc, base);
>        } else {
> --
> 1.7.9.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net

Re: [PATCH 30/37] drm/i915: disable rc6 on haswell for now

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Mar 21, 2012 at 10:10 PM, Eugeni Dodonov
<eugeni.dodonov@intel.com> wrote:
> This needs proper enablement to avoid machine hangs, so let's just avoid
> it for now.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |    4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2c5b953..f7dbcab 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8275,6 +8275,10 @@ static bool intel_enable_rc6(struct drm_device *dev)
>        if (INTEL_INFO(dev)->gen == 5)
>                return 0;
>
> +       /* Sorry Haswell, no RC6 for you for now. */
> +       if (IS_HASWELL(dev))
> +               return 0;
> +
>        /*
>         * Disable rc6 on Sandybridge
>         */
> --
> 1.7.9.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net

Re: [PATCH 19/37] drm/i915: add LCPLL control registers

[Rodrigo Vivi]

that's true!

On Mon, Mar 26, 2012 at 2:46 PM, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Mon, Mar 26, 2012 at 02:42:30PM -0300, Rodrigo Vivi wrote:
>>  LCPLL_PLL_ENABLE should be  (0<<31)\
>
> I that case I think we should name it LCPLL_PLL_DISABLE (and use (1<<31)
> obviously).
> -Daniel
>
>>
>> Otherwise
>>
>> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
>>
>> On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
>> <eugeni.dodonov@intel.com> wrote:
>> > Those are used to control the display core clock.
>> >
>> > Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
>> > ---
>> >  drivers/gpu/drm/i915/i915_reg.h |    7 +++++++
>> >  1 file changed, 7 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> > index 03fb10d..fa9e3a8 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -4014,4 +4014,11 @@
>> >  #define GTCCLK_EN                              0xC6030
>> >  #define  GTCCLK_EN_ENABLE              (1<<0)
>> >
>> > +/* LCPLL Control */
>> > +#define LCPLL_CTL                              0x130040
>> > +#define  LCPLL_PLL_ENABLE              (1<<31)
>> > +#define  LCPLL_PLL_LOCK                        (1<<30)
>> > +#define  LCPLL_CD_CLOCK_DISABLE        (1<<25)
>> > +#define  LCPLL_CD2X_CLOCK_DISABLE      (1<<23)
>> > +
>> >  #endif /* _I915_REG_H_ */
>> > --
>> > 1.7.9.2
>> >
>> > _______________________________________________
>> > Intel-gfx mailing list
>> > Intel-gfx@lists.freedesktop.org
>> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>>
>>
>> --
>> Rodrigo Vivi
>> Blog: http://blog.vivi.eng.br
>> GPG: 0x905BE242 @ wwwkeys.pgp.net
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Mail: daniel@ffwll.ch
> Mobile: +41 (0)79 365 57 48



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net

Re: [PATCH 12/37] drm/i915: add SBI registers

[Rodrigo Vivi]

and here can be

SBI_BUSY 0x1<<0
and SBI_RESPONSE_UNSUCCESSFUL 0x1<<1

On Mon, Mar 26, 2012 at 2:48 PM, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
> Ops, actually I'm in doubt about this one, for me:
>
> SBI_RESPONSE  should be  (0x0<<1)
> SBI_READY  should be    (0x0<<0)
>
> let's double check this togheter, otherwise:
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
>
> On Mon, Mar 26, 2012 at 2:40 PM, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
>> * indentation
>> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
>>
>> On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
>> <eugeni.dodonov@intel.com> wrote:
>>> Those are responsible for the Sideband Interface programming.
>>>
>>> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
>>> ---
>>>  drivers/gpu/drm/i915/i915_reg.h |   10 ++++++++++
>>>  1 file changed, 10 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>> index 0af47b4..4ee8965 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -3947,4 +3947,14 @@
>>>  #define DDI_BUF_TRANS_D                                0x64F20
>>>  #define DDI_BUF_TRANS_E                                0x64F80
>>>
>>> +/* Sideband Interface (SBI) is programmed indirectly, via
>>> + * SBI_ADDR, which contains the register offset; and SBI_DATA,
>>> + * which contains the payload */
>>> +#define SBI_ADDR                               0xC6000
>>> +#define SBI_DATA                               0xC6004
>>> +#define SBI_CTL_STAT                   0xC6008
>>> +#define  SBI_CTL_OP_CRRD               (0x6<<8)
>>> +#define  SBI_CTL_OP_CRWR               (0x7<<8)
>>> +#define  SBI_RESPONSE                  (0x1<<1)
>>> +#define  SBI_READY                             (0x1<<0)
>>>  #endif /* _I915_REG_H_ */
>>> --
>>> 1.7.9.2
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>>
>>
>> --
>> Rodrigo Vivi
>> Blog: http://blog.vivi.eng.br
>> GPG: 0x905BE242 @ wwwkeys.pgp.net
>
>
>
> --
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br
> GPG: 0x905BE242 @ wwwkeys.pgp.net



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net

Re: [PATCH 24/37] drm/i915: share forcewaking code between IVB and HSW

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
<eugeni.dodonov@intel.com> wrote:
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 24a0a6c..27ab70d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8906,7 +8906,7 @@ static void intel_init_display(struct drm_device *dev)
>                dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
>
>                /* IVB configs may use multi-threaded forcewake */
> -               if (IS_IVYBRIDGE(dev)) {
> +               if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
>                        u32     ecobus;
>
>                        /* A small trick here - if the bios hasn't configured MT forcewake,
> --
> 1.7.9.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net

Re: [PATCH 05/37] drm/i915: add support for power wells

[Eugeni Dodonov]

[-- Attachment #1.1: Type: text/plain, Size: 625 bytes --]

On Mon, Mar 26, 2012 at 14:32, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:

> Like in this patch, the defines indentation in some patches in this
> series sounds strange, wrong, or at least different from the one
> already in use.
>
> So, since I don't know if we should care about indentation now, for
> those patches I'll just mark like this:
>
> * indentation
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
>

The identation is different between registers themselves (e.g.,
0xSOMETHING) and the bits we use in those registers (e.g., (1<<31)). So
this is on purpose.

-- 
Eugeni Dodonov
<http://eugeni.dodonov.net/>

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Re: [PATCH 06/37] drm/i915: add DDI registers

[Eugeni Dodonov]

[-- Attachment #1.1: Type: text/plain, Size: 343 bytes --]

On Mon, Mar 26, 2012 at 14:35, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:

> *indentation
> and it is missing
> #define  PIPE_DDI_MODE_SELECT_DP_MST  (3<<24)
>
> Otherwise:
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
>

We are not using this bit, this is why I am not exposing it...

-- 
Eugeni Dodonov
<http://eugeni.dodonov.net/>

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Re: [PATCH 35/37] drm/i915: program iCLKIP on Lynx Point

[Rodrigo Vivi]

Yeah, intel_display is becoming so huge.

Paulo, Jesse and I talked a bit about this in osts and I think a reorg
here would be good. What do you think about splitting it in something
similar to omap displays (drivers/video/omap)?

On Thu, Mar 22, 2012 at 7:31 AM, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Wed, Mar 21, 2012 at 10:10:10PM -0300, Eugeni Dodonov wrote:
>> The iCLKIP clock is used to drive the VGA pixel clock on the PCH. In order
>> to do so, it must be programmed to properly do the clock ticks according
>> to the divisor, phase direction, phase increments and a special auxiliary
>> divisor for 20MHz clock.
>>
>> Those values can be programmed individually, by doing some math; or we
>> could use a pre-defined table of values for each modeset. For speed and
>> simplification, the idea was to just adopt the table of valid pixel clocks
>> and select the matching iCLKIP values from there.
>>
>> As a possible idea for the future, it would be possible to add a fallback
>> and calculate those values manually in case no match is found. But I don't
>> think we'll encounter a mode not covered by those table, and VGA is pretty
>> much going away in the future anyway.
>>
>> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
>
> With stuff like this, intel_display.c has definitely grown into the
> unmanageable territory. Along Jesse's suggestion I think it would make
> sense to split out the pch and gmch modeset stuff into separate files (and
> leave all the other things like initialization, clock gating watermark
> functions, pageflip, cursors, power crap and what not else in
> intel_display.c). We could call these new files intel_pch_modeset.c and
> intel_gmch_modeset.c, they'd contain the respective crtc_mode_set function
> plus all associated support code.
>
> I'll leave this to you and Jesse to decide whether it makes sense as
> proposed and when you want to move the code. But I think we need to
> slaugther this dragon and cut it into more manageable pieces now.
>
> Jesse?
>
> Yours, Daniel
>
>> ---
>>  drivers/gpu/drm/i915/intel_display.c |  309 ++++++++++++++++++++++++++++++++++
>>  1 file changed, 309 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 5f6cb35..a37e0b7 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -2761,6 +2761,312 @@ static const long hsw_ddi_buf_ctl_values[] = {
>>       DDI_BUF_EMP_800MV_3_5DB_HSW
>>  };
>>
>> +/* Available pixel clock values */
>> +struct iclk_vga_clock {
>> +     u32 clock;
>> +     u16 auxdiv;
>> +     u16 divsel;
>> +     u16 phasedir;
>> +     u16 phaseinc;
>> +};
>> +
>> +static const struct iclk_vga_clock iclk_vga_clock_table[] = {
>> +     {20000, 1,      0x41,   0,      0x20},  /* 20000 ppm=0 */
>> +     {21000, 0,      0x7E,   0,      0x25},  /* 20999 ppm=-53 */
>> +     {21912, 0,      0x79,   0,      0x0E},  /* 21912 ppm=12 */
>> +     {22000, 0,      0x78,   0,      0x2F},  /* 21999 ppm=-58 */
>> +     {23000, 0,      0x73,   0,      0x19},  /* 23000 ppm=6 */
>> +     {24000, 0,      0x6E,   0,      0x20},  /* 24000 ppm=0 */
>> +     {25000, 0,      0x6A,   0,      0x00},  /* 25000 ppm=0 */
>> +     {25175, 0,      0x69,   0,      0x10},  /* 25175 ppm=-7 */
>> +     {25200, 0,      0x69,   0,      0x09},  /* 25201 ppm=21 */
>> +     {26000, 0,      0x66,   1,      0x0A},  /* 26001 ppm=24 */
>> +     {27000, 0,      0x62,   0,      0x00},  /* 27000 ppm=0 */
>> +     {27027, 0,      0x62,   1,      0x06},  /* 27025 ppm=-62 */
>> +     {27500, 0,      0x60,   0,      0x0C},  /* 27498 ppm=-58 */
>> +     {28000, 0,      0x5E,   0,      0x1B},  /* 28002 ppm=70 */
>> +     {28320, 0,      0x5D,   0,      0x16},  /* 28319 ppm=-50 */
>> +     {28322, 0,      0x5D,   0,      0x15},  /* 28323 ppm=44 */
>> +     {29000, 0,      0x5B,   0,      0x07},  /* 28998 ppm=-64 */
>> +     {30000, 0,      0x58,   0,      0x00},  /* 30000 ppm=0 */
>> +     {31000, 0,      0x55,   0,      0x06},  /* 31001 ppm=35 */
>> +     {31500, 0,      0x54,   1,      0x12},  /* 31498 ppm=-53 */
>> +     {32000, 0,      0x52,   0,      0x18},  /* 32000 ppm=0 */
>> +     {32500, 0,      0x51,   0,      0x05},  /* 32500 ppm=-15 */
>> +     {33000, 0,      0x50,   1,      0x0C},  /* 33002 ppm=70 */
>> +     {34000, 0,      0x4D,   0,      0x1A},  /* 34002 ppm=70 */
>> +     {35000, 0,      0x4B,   0,      0x09},  /* 35001 ppm=29 */
>> +     {35500, 0,      0x4A,   0,      0x04},  /* 35497 ppm=-82 */
>> +     {36000, 0,      0x49,   0,      0x00},  /* 36000 ppm=0 */
>> +     {37000, 0,      0x47,   1,      0x02},  /* 37002 ppm=58 */
>> +     {38000, 0,      0x45,   0,      0x03},  /* 38003 ppm=82 */
>> +     {39000, 0,      0x43,   0,      0x0F},  /* 38998 ppm=-53 */
>> +     {40000, 0,      0x41,   0,      0x20},  /* 40000 ppm=0 */
>> +     {40500, 0,      0x41,   1,      0x15},  /* 40497 ppm=-79 */
>> +     {40541, 0,      0x41,   1,      0x1A},  /* 40544 ppm=95 */
>> +     {41000, 0,      0x40,   1,      0x09},  /* 40996 ppm=-87 */
>> +     {41540, 0,      0x3F,   0,      0x00},  /* 41538 ppm=-38 */
>> +     {42000, 0,      0x3E,   0,      0x12},  /* 42003 ppm=70 */
>> +     {43000, 0,      0x3D,   1,      0x0D},  /* 42996 ppm=-99 */
>> +     {43163, 0,      0x3D,   1,      0x1D},  /* 43168 ppm=108 */
>> +     {44000, 0,      0x3B,   0,      0x17},  /* 44003 ppm=70 */
>> +     {44900, 0,      0x3A,   0,      0x09},  /* 44895 ppm=-117 */
>> +     {45000, 0,      0x3A,   0,      0x00},  /* 45000 ppm=0 */
>> +     {46000, 0,      0x39,   1,      0x13},  /* 45994 ppm=-128 */
>> +     {47000, 0,      0x37,   0,      0x1D},  /* 46995 ppm=-110 */
>> +     {48000, 0,      0x36,   0,      0x10},  /* 48000 ppm=0 */
>> +     {49000, 0,      0x35,   0,      0x07},  /* 48993 ppm=-134 */
>> +     {49500, 0,      0x35,   1,      0x1D},  /* 49499 ppm=-27 */
>> +     {50000, 0,      0x34,   0,      0x00},  /* 50000 ppm=0 */
>> +     {51000, 0,      0x33,   1,      0x04},  /* 51004 ppm=70 */
>> +     {52000, 0,      0x32,   1,      0x05},  /* 52001 ppm=24 */
>> +     {52406, 0,      0x32,   1,      0x1F},  /* 52411 ppm=101 */
>> +     {53000, 0,      0x31,   1,      0x04},  /* 53006 ppm=116 */
>> +     {54000, 0,      0x30,   0,      0x00},  /* 54000 ppm=0 */
>> +     {54054, 0,      0x30,   1,      0x03},  /* 54051 ppm=-62 */
>> +     {55000, 0,      0x2F,   0,      0x06},  /* 54997 ppm=-58 */
>> +     {56000, 0,      0x2E,   0,      0x0E},  /* 55995 ppm=-93 */
>> +     {56250, 0,      0x2E,   0,      0x00},  /* 56250 ppm=0 */
>> +     {57000, 0,      0x2D,   0,      0x18},  /* 56992 ppm=-139 */
>> +     {58000, 0,      0x2D,   1,      0x1D},  /* 58006 ppm=105 */
>> +     {59000, 0,      0x2C,   1,      0x0F},  /* 58996 ppm=-64 */
>> +     {60000, 0,      0x2B,   0,      0x00},  /* 60000 ppm=0 */
>> +     {61000, 0,      0x2A,   0,      0x11},  /* 60995 ppm=-76 */
>> +     {62000, 0,      0x2A,   1,      0x1D},  /* 62002 ppm=35 */
>> +     {63000, 0,      0x29,   1,      0x09},  /* 62997 ppm=-53 */
>> +     {64000, 0,      0x28,   0,      0x0C},  /* 64000 ppm=0 */
>> +     {65000, 0,      0x28,   1,      0x1E},  /* 65011 ppm=174 */
>> +     {66000, 0,      0x27,   1,      0x06},  /* 66005 ppm=70 */
>> +     {66667, 0,      0x26,   0,      0x20},  /* 66667 ppm=-5 */
>> +     {67000, 0,      0x26,   0,      0x13},  /* 67003 ppm=41 */
>> +     {68000, 0,      0x26,   1,      0x13},  /* 68005 ppm=70 */
>> +     {68179, 0,      0x26,   1,      0x19},  /* 68166 ppm=-196 */
>> +     {69000, 0,      0x25,   0,      0x08},  /* 69010 ppm=139 */
>> +     {70000, 0,      0x25,   1,      0x1B},  /* 69988 ppm=-174 */
>> +     {71000, 0,      0x24,   0,      0x02},  /* 70994 ppm=-82 */
>> +     {72000, 0,      0x23,   0,      0x20},  /* 72000 ppm=0 */
>> +     {73000, 0,      0x23,   1,      0x01},  /* 73004 ppm=53 */
>> +     {74000, 0,      0x22,   0,      0x1F},  /* 74004 ppm=58 */
>> +     {74175, 0,      0x22,   0,      0x1A},  /* 74163 ppm=-161 */
>> +     {74250, 0,      0x22,   0,      0x17},  /* 74259 ppm=118 */
>> +     {74481, 0,      0x22,   0,      0x10},  /* 74483 ppm=24 */
>> +     {75000, 0,      0x22,   0,      0x00},  /* 75000 ppm=0 */
>> +     {76000, 0,      0x22,   1,      0x1E},  /* 75989 ppm=-139 */
>> +     {77000, 0,      0x21,   0,      0x04},  /* 77005 ppm=70 */
>> +     {78000, 0,      0x21,   1,      0x19},  /* 78014 ppm=174 */
>> +     {78750, 0,      0x20,   0,      0x12},  /* 78760 ppm=131 */
>> +     {79000, 0,      0x20,   0,      0x0B},  /* 79012 ppm=157 */
>> +     {80000, 0,      0x20,   1,      0x10},  /* 80000 ppm=0 */
>> +     {81000, 0,      0x1F,   0,      0x15},  /* 81013 ppm=157 */
>> +     {81081, 0,      0x1F,   0,      0x13},  /* 81089 ppm=95 */
>> +     {81624, 0,      0x1F,   0,      0x05},  /* 81625 ppm=12 */
>> +     {82000, 0,      0x1F,   1,      0x05},  /* 82012 ppm=151 */
>> +     {83000, 0,      0x1F,   1,      0x1E},  /* 82997 ppm=-35 */
>> +     {83950, 0,      0x1E,   0,      0x0A},  /* 83965 ppm=179 */
>> +     {84000, 0,      0x1E,   0,      0x09},  /* 84006 ppm=70 */
>> +     {85000, 0,      0x1E,   1,      0x0F},  /* 84998 ppm=-29 */
>> +     {86000, 0,      0x1D,   0,      0x19},  /* 86013 ppm=151 */
>> +     {87000, 0,      0x1D,   0,      0x02},  /* 87009 ppm=105 */
>> +     {88000, 0,      0x1D,   1,      0x14},  /* 87984 ppm=-186 */
>> +     {89000, 0,      0x1C,   0,      0x16},  /* 88980 ppm=-220 */
>> +     {90000, 0,      0x1C,   0,      0x00},  /* 90000 ppm=0 */
>> +     {91000, 0,      0x1C,   1,      0x15},  /* 90995 ppm=-53 */
>> +     {92000, 0,      0x1B,   0,      0x16},  /* 92013 ppm=139 */
>> +     {93000, 0,      0x1B,   0,      0x02},  /* 93003 ppm=35 */
>> +     {94000, 0,      0x1B,   1,      0x12},  /* 94015 ppm=163 */
>> +     {94500, 0,      0x1B,   1,      0x1B},  /* 94478 ppm=-235 */
>> +     {95000, 0,      0x1A,   0,      0x1B},  /* 94997 ppm=-29 */
>> +     {95654, 0,      0x1A,   0,      0x0F},  /* 95628 ppm=-271 */
>> +     {96000, 0,      0x1A,   0,      0x08},  /* 96000 ppm=0 */
>> +     {97000, 0,      0x1A,   1,      0x0B},  /* 97024 ppm=249 */
>> +     {98000, 0,      0x1A,   1,      0x1D},  /* 98015 ppm=151 */
>> +     {99000, 0,      0x19,   0,      0x11},  /* 99026 ppm=261 */
>> +     {100000,        0,      0x19,   0,      0x00},  /* 100000 ppm=0 */
>> +     {101000,        0,      0x19,   1,      0x11},  /* 100994 ppm=-64 */
>> +     {102000,        0,      0x18,   0,      0x1E},  /* 102007 ppm=70 */
>> +     {103000,        0,      0x18,   0,      0x0E},  /* 102980 ppm=-197 */
>> +     {104000,        0,      0x18,   1,      0x02},  /* 103971 ppm=-278 */
>> +     {105000,        0,      0x18,   1,      0x12},  /* 104982 ppm=-174 */
>> +     {106000,        0,      0x17,   0,      0x1E},  /* 106012 ppm=116 */
>> +     {107000,        0,      0x17,   0,      0x0F},  /* 106997 ppm=-29 */
>> +     {107214,        0,      0x17,   0,      0x0C},  /* 107196 ppm=-168 */
>> +     {108000,        0,      0x17,   0,      0x00},  /* 108000 ppm=0 */
>> +     {109000,        0,      0x17,   1,      0x0F},  /* 109022 ppm=203 */
>> +     {110000,        0,      0x17,   1,      0x1D},  /* 109994 ppm=-58 */
>> +     {110013,        0,      0x17,   1,      0x1D},  /* 109994 ppm=-177 */
>> +     {111000,        0,      0x16,   0,      0x15},  /* 110983 ppm=-157 */
>> +     {111263,        0,      0x16,   0,      0x11},  /* 111269 ppm=55 */
>> +     {111375,        0,      0x16,   0,      0x10},  /* 111340 ppm=-313 */
>> +     {112000,        0,      0x16,   0,      0x07},  /* 111990 ppm=-93 */
>> +     {113000,        0,      0x16,   1,      0x07},  /* 113015 ppm=134 */
>> +     {113309,        0,      0x16,   1,      0x0B},  /* 113311 ppm=22 */
>> +     {113100,        0,      0x16,   1,      0x08},  /* 113089 ppm=-98 */
>> +     {114000,        0,      0x16,   1,      0x14},  /* 113984 ppm=-139 */
>> +     {115000,        0,      0x15,   0,      0x1F},  /* 114970 ppm=-261 */
>> +     {116000,        0,      0x15,   0,      0x12},  /* 115973 ppm=-232 */
>> +     {117000,        0,      0x15,   0,      0x05},  /* 116994 ppm=-53 */
>> +     {118000,        0,      0x15,   1,      0x08},  /* 118033 ppm=278 */
>> +     {119000,        0,      0x15,   1,      0x14},  /* 119008 ppm=70 */
>> +     {119651,        0,      0x15,   1,      0x1C},  /* 119668 ppm=139 */
>> +     {120000,        0,      0x14,   0,      0x20},  /* 120000 ppm=0 */
>> +     {121000,        0,      0x14,   0,      0x14},  /* 121008 ppm=70 */
>> +     {122000,        0,      0x14,   0,      0x08},  /* 122034 ppm=278 */
>> +     {122614,        0,      0x14,   0,      0x01},  /* 122640 ppm=214 */
>> +     {123000,        0,      0x14,   1,      0x03},  /* 122989 ppm=-87 */
>> +     {123379,        0,      0x14,   1,      0x07},  /* 123340 ppm=-313 */
>> +     {124000,        0,      0x14,   1,      0x0E},  /* 123960 ppm=-324 */
>> +     {125000,        0,      0x14,   1,      0x1A},  /* 125036 ppm=290 */
>> +     {126000,        0,      0x13,   0,      0x1B},  /* 126039 ppm=313 */
>> +     {127000,        0,      0x13,   0,      0x11},  /* 126965 ppm=-272 */
>> +     {128000,        0,      0x13,   0,      0x06},  /* 128000 ppm=0 */
>> +     {129000,        0,      0x13,   1,      0x04},  /* 128955 ppm=-348 */
>> +     {129859,        0,      0x13,   1,      0x0D},  /* 129827 ppm=-245 */
>> +     {130000,        0,      0x13,   1,      0x0F},  /* 130023 ppm=174 */
>> +     {131000,        0,      0x13,   1,      0x19},  /* 131008 ppm=64 */
>> +     {131850,        0,      0x12,   0,      0x1F},  /* 131808 ppm=-321 */
>> +     {132000,        0,      0x12,   0,      0x1D},  /* 132009 ppm=70 */
>> +     {133000,        0,      0x12,   0,      0x13},  /* 133025 ppm=192 */
>> +     {133330,        0,      0x12,   0,      0x10},  /* 133333 ppm=26 */
>> +     {134000,        0,      0x12,   0,      0x0A},  /* 133953 ppm=-348 */
>> +     {135000,        0,      0x12,   0,      0x00},  /* 135000 ppm=0 */
>> +     {136000,        0,      0x12,   1,      0x09},  /* 135956 ppm=-324 */
>> +     {137000,        0,      0x12,   1,      0x13},  /* 137034 ppm=249 */
>> +     {138000,        0,      0x12,   1,      0x1C},  /* 138019 ppm=139 */
>> +     {139000,        0,      0x11,   0,      0x1B},  /* 139019 ppm=134 */
>> +     {139050,        0,      0x11,   0,      0x1B},  /* 139019 ppm=-227 */
>> +     {139054,        0,      0x11,   0,      0x1B},  /* 139019 ppm=-256 */
>> +     {140000,        0,      0x11,   0,      0x12},  /* 140032 ppm=232 */
>> +     {141000,        0,      0x11,   0,      0x0A},  /* 140946 ppm=-382 */
>> +     {142000,        0,      0x11,   0,      0x01},  /* 141988 ppm=-82 */
>> +     {143000,        0,      0x11,   1,      0x08},  /* 143046 ppm=325 */
>> +     {143472,        0,      0x11,   1,      0x0C},  /* 143522 ppm=346 */
>> +     {144000,        0,      0x11,   1,      0x10},  /* 144000 ppm=0 */
>> +     {145000,        0,      0x11,   1,      0x18},  /* 144966 ppm=-232 */
>> +     {146000,        0,      0x10,   0,      0x20},  /* 145946 ppm=-371 */
>> +     {147000,        0,      0x10,   0,      0x18},  /* 146939 ppm=-417 */
>> +     {147891,        0,      0x10,   0,      0x10},  /* 147945 ppm=367 */
>> +     {148000,        0,      0x10,   0,      0x10},  /* 147945 ppm=-371 */
>> +     {148350,        0,      0x10,   0,      0x0D},  /* 148326 ppm=-161 */
>> +     {148500,        0,      0x10,   0,      0x0C},  /* 148454 ppm=-313 */
>> +     {149000,        0,      0x10,   0,      0x08},  /* 148966 ppm=-232 */
>> +     {150000,        0,      0x10,   0,      0x00},  /* 150000 ppm=0 */
>> +     {151000,        0,      0x10,   1,      0x08},  /* 151049 ppm=325 */
>> +     {152000,        0,      0x10,   1,      0x0F},  /* 151979 ppm=-139 */
>> +     {152280,        0,      0x10,   1,      0x11},  /* 152247 ppm=-219 */
>> +     {153000,        0,      0x10,   1,      0x17},  /* 153056 ppm=365 */
>> +     {154000,        0,      0x10,   1,      0x1E},  /* 154011 ppm=70 */
>> +     {155000,        0,      0x0F,   0,      0x1B},  /* 154978 ppm=-145 */
>> +     {156000,        0,      0x0F,   0,      0x14},  /* 155957 ppm=-278 */
>> +     {157000,        0,      0x0F,   0,      0x0D},  /* 156948 ppm=-330 */
>> +     {157500,        0,      0x0F,   0,      0x09},  /* 157521 ppm=131 */
>> +     {158000,        0,      0x0F,   0,      0x06},  /* 157952 ppm=-301 */
>> +     {159000,        0,      0x0F,   1,      0x01},  /* 158970 ppm=-191 */
>> +     {160000,        0,      0x0F,   1,      0x08},  /* 160000 ppm=0 */
>> +     {161000,        0,      0x0F,   1,      0x0F},  /* 161044 ppm=273 */
>> +     {162000,        0,      0x0F,   1,      0x15},  /* 161949 ppm=-313 */
>> +     {163000,        0,      0x0F,   1,      0x1C},  /* 163019 ppm=116 */
>> +     {164000,        0,      0x0E,   0,      0x1E},  /* 163947 ppm=-324 */
>> +     {165000,        0,      0x0E,   0,      0x17},  /* 165043 ppm=261 */
>> +     {166000,        0,      0x0E,   0,      0x11},  /* 165994 ppm=-35 */
>> +     {167000,        0,      0x0E,   0,      0x0B},  /* 166957 ppm=-261 */
>> +     {168000,        0,      0x0E,   0,      0x05},  /* 167930 ppm=-417 */
>> +     {169000,        0,      0x0E,   1,      0x02},  /* 169080 ppm=475 */
>> +     {169128,        0,      0x0E,   1,      0x02},  /* 169080 ppm=-283 */
>> +     {170000,        0,      0x0E,   1,      0x08},  /* 170079 ppm=464 */
>> +     {171000,        0,      0x0E,   1,      0x0D},  /* 170920 ppm=-469 */
>> +     {172000,        0,      0x0E,   1,      0x13},  /* 171940 ppm=-348 */
>> +     {172800,        0,      0x0E,   1,      0x18},  /* 172800 ppm=0 */
>> +     {173000,        0,      0x0E,   1,      0x19},  /* 172973 ppm=-157 */
>> +     {174000,        0,      0x0E,   1,      0x1F},  /* 174018 ppm=105 */
>> +     {174787,        0,      0x0D,   0,      0x1D},  /* 174722 ppm=-373 */
>> +     {175000,        0,      0x0D,   0,      0x1B},  /* 175076 ppm=435 */
>> +     {175500,        0,      0x0D,   0,      0x19},  /* 175431 ppm=-391 */
>> +     {176000,        0,      0x0D,   0,      0x16},  /* 175967 ppm=-186 */
>> +     {177000,        0,      0x0D,   0,      0x10},  /* 177049 ppm=278 */
>> +     {178000,        0,      0x0D,   0,      0x0B},  /* 177961 ppm=-220 */
>> +     {179000,        0,      0x0D,   0,      0x05},  /* 179067 ppm=377 */
>> +     {180000,        0,      0x0D,   0,      0x00},  /* 180000 ppm=0 */
>> +};
>> +
>> +/* Program iCLKIP clock to the desired frequency */
>> +static void lpt_program_iclkip(struct drm_crtc *crtc)
>> +{
>> +     struct drm_device *dev = crtc->dev;
>> +     struct drm_i915_private *dev_priv = dev->dev_private;
>> +     u32 auxdiv=0, divsel=0, phasedir=0, phaseinc=0, valid=0;
>> +     u32 temp, i;
>> +
>> +     /* Ungate pixel clock */
>> +     I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
>> +
>> +     /* Disable SSCCTL */
>> +     SBI_WRITE(dev_priv, SBI_SSCCTL6,
>> +                             SBI_READ(dev_priv, SBI_SSCCTL6) |
>> +                                     SBI_SSCCTL_DISABLE);
>> +
>> +     /* Calculating clock values for iCLKIP */
>> +     for (i=0; i < ARRAY_SIZE(iclk_vga_clock_table); i++) {
>> +             if (crtc->mode.clock == iclk_vga_clock_table[i].clock) {
>> +                     DRM_INFO("Found clock settings for %dKHz refresh rate\n",
>> +                                     crtc->mode.clock);
>> +
>> +                     auxdiv = iclk_vga_clock_table[i].auxdiv;
>> +                     divsel = iclk_vga_clock_table[i].divsel;
>> +                     phasedir = iclk_vga_clock_table[i].phasedir;
>> +                     phaseinc = iclk_vga_clock_table[i].phaseinc;
>> +
>> +                     valid = 1;
>> +
>> +                     break;
>> +             }
>> +     }
>> +
>> +     if (!valid) {
>> +             DRM_ERROR("Unable to find iCLKIP clock settings for %dKHz refresh rate\n",
>> +                             crtc->mode.clock);
>> +             return;
>> +     }
>> +
>> +     /* Program SSCDIVINTPHASE6 with values which HW team uses */
>> +     DRM_DEBUG("Programming SSCDIVINTPHASE for %dKHz: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
>> +                     crtc->mode.clock,
>> +                     auxdiv,
>> +                     divsel,
>> +                     phasedir,
>> +                     phaseinc);
>> +
>> +     /* Program SSCDIVINTPHASE6 */
>> +     temp = SBI_READ(dev_priv, SBI_SSCDIVINTPHASE6);
>> +     temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
>> +     temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
>> +     temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
>> +     temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
>> +     temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
>> +     temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
>> +
>> +     SBI_WRITE(dev_priv,
>> +                     SBI_SSCDIVINTPHASE6,
>> +                     temp);
>> +
>> +     /* Program SSCAUXDIV */
>> +     SBI_WRITE(dev_priv,
>> +                     SBI_SSCAUXDIV6,
>> +                             SBI_READ(dev_priv, SBI_SSCAUXDIV6) |
>> +                                     SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv));
>> +
>> +
>> +     /* Enable modulator and associated divider */
>> +     SBI_WRITE(dev_priv, SBI_SSCCTL6,
>> +                             SBI_READ(dev_priv, SBI_SSCCTL6) &
>> +                                     ~SBI_SSCCTL_DISABLE);
>> +
>> +     /* Wait for initialization time */
>> +     udelay(50);
>> +
>> +     /* Gate pixel clock */
>> +     I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
>> +}
>> +
>>
>>  /* Link training for HSW parts */
>>  static void hsw_fdi_link_train(struct drm_crtc *crtc)
>> @@ -3182,6 +3488,9 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>>               /* DDIE clock is recommented for FDI connections */
>>               I915_WRITE(PIPE_CLK_SEL(pipe),
>>                               PIPE_CLK_SEL_DDIE);
>> +
>> +             /* Program iCLKIP */
>> +             lpt_program_iclkip(crtc);
>>       }
>>
>>       /* set transcoder timing, panel must allow it */
>> --
>> 1.7.9.2
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Mail: daniel@ffwll.ch
> Mobile: +41 (0)79 365 57 48
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net

Re: [PATCH 06/37] drm/i915: add DDI registers

[Rodrigo Vivi]

ah ok, no problem than...  I just imagine that this would be useful
because in other places you mentioned the DP MST mode...

On Mon, Mar 26, 2012 at 2:58 PM, Eugeni Dodonov <eugeni@dodonov.net> wrote:
> On Mon, Mar 26, 2012 at 14:35, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
>>
>> *indentation
>> and it is missing
>> #define  PIPE_DDI_MODE_SELECT_DP_MST  (3<<24)
>>
>> Otherwise:
>> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
>
>
> We are not using this bit, this is why I am not exposing it...
>
> --
> Eugeni Dodonov
>



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net

Re: [PATCH 10/37] drm/i915: add definition of LPT FDI port width registers

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
<eugeni.dodonov@intel.com> wrote:
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |    3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2927460..b732aa1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3473,6 +3473,9 @@
>  #define  FDI_LINK_TRAIN_PATTERN_IDLE_CPT       (2<<8)
>  #define  FDI_LINK_TRAIN_NORMAL_CPT             (3<<8)
>  #define  FDI_LINK_TRAIN_PATTERN_MASK_CPT       (3<<8)
> +/* LPT */
> +#define  LPT_FDI_PORT_WIDTH_1X          (0<<19)
> +#define  LPT_FDI_PORT_WIDTH_2X          (1<<19)
>
>  #define _FDI_RXA_MISC            0xf0010
>  #define _FDI_RXB_MISC            0xf1010
> --
> 1.7.9.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net

Re: [PATCH 02/37] drm/i915: add support for LynxPoint PCH

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Wed, Mar 21, 2012 at 10:09 PM, Eugeni Dodonov
<eugeni.dodonov@intel.com> wrote:
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c |    4 ++++
>  drivers/gpu/drm/i915/i915_drv.h |    2 ++
>  2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index d4f542b..5fe9d62 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -326,6 +326,7 @@ MODULE_DEVICE_TABLE(pci, pciidlist);
>  #define INTEL_PCH_IBX_DEVICE_ID_TYPE   0x3b00
>  #define INTEL_PCH_CPT_DEVICE_ID_TYPE   0x1c00
>  #define INTEL_PCH_PPT_DEVICE_ID_TYPE   0x1e00
> +#define INTEL_PCH_LPT_DEVICE_ID_TYPE   0x8c00
>
>  void intel_detect_pch(struct drm_device *dev)
>  {
> @@ -354,6 +355,9 @@ void intel_detect_pch(struct drm_device *dev)
>                                /* PantherPoint is CPT compatible */
>                                dev_priv->pch_type = PCH_CPT;
>                                DRM_DEBUG_KMS("Found PatherPoint PCH\n");
> +                       } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
> +                               dev_priv->pch_type = PCH_LPT;
> +                               DRM_DEBUG_KMS("Found LynxPoint PCH\n");
>                        }
>                }
>                pci_dev_put(pch);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 9a99ef1..49488e1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -292,6 +292,7 @@ enum no_fbc_reason {
>  enum intel_pch {
>        PCH_IBX,        /* Ibexpeak PCH */
>        PCH_CPT,        /* Cougarpoint PCH */
> +       PCH_LPT,        /* Lynxpoint PCH */
>  };
>
>  #define QUIRK_PIPEA_FORCE (1<<0)
> @@ -1050,6 +1051,7 @@ struct drm_i915_file_private {
>  #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
>
>  #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
> +#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
>  #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
>  #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
>
> --
> 1.7.9.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net

Re: [PATCH 11/37] drm/i915: add definition of DDI buffer translations regs

[Daniel Vetter]

On Wed, Mar 21, 2012 at 10:09:46PM -0300, Eugeni Dodonov wrote:
> Those registers are used to train DDI buffer translations for each link
> type.
> 
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>

some quick private discussion releaved that the A-E in these defines are
also per-port. So I think we also need to rebase these on top of a port
enum with a DDI_BUF_TRANS(port) macros instead.
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_reg.h |    7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b732aa1..0af47b4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3940,4 +3940,11 @@
>  #define  DDI_PORT_WIDTH_X4				(3<<1)
>  #define  DDI_INIT_DISPLAY_DETECTED		(1<<0)
>  
> +/* DDI Buffer Translations */
> +#define DDI_BUF_TRANS_A				0x64E00
> +#define DDI_BUF_TRANS_B				0x64E60
> +#define DDI_BUF_TRANS_C				0x64EC0
> +#define DDI_BUF_TRANS_D				0x64F20
> +#define DDI_BUF_TRANS_E				0x64F80
> +
>  #endif /* _I915_REG_H_ */
> -- 
> 1.7.9.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

Re: [PATCH 35/37] drm/i915: program iCLKIP on Lynx Point

[Jesse Barnes]

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On Mon, 26 Mar 2012 15:00:14 -0300
Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:

> Yeah, intel_display is becoming so huge.
> 
> Paulo, Jesse and I talked a bit about this in osts and I think a reorg
> here would be good. What do you think about splitting it in something
> similar to omap displays (drivers/video/omap)?

Yeah more splitting is definitely desired.  We already have per-output
stuff like OMAP appears to have, but I think at the very least
intel_display.c should be split between PCH and non-PCH parts to start
with.

-- 
Jesse Barnes, Intel Open Source Technology Center

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Re: [PATCH 31/37] drm/i915: enable PCH earlier

[Jesse Barnes]

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On Thu, 22 Mar 2012 11:05:22 +0000
Chris Wilson <chris@chris-wilson.co.uk> wrote:

> On Wed, 21 Mar 2012 22:10:06 -0300, Eugeni Dodonov <eugeni.dodonov@intel.com> wrote:
> > The modesetting sequence for PCH-related connections mentions that the
> > order of plane/pipe enablement could happen either before of after PCH
> > enablement.
> > 
> > With LPT, however, we need to enable some things earlier to be able to
> > talk to PCH. So let's do it a bit in advance.
> 
> Touching modesetting sequence is a nerve racking experience. Can we
> arrange to have this patch tested by itself, right now?

Double plus agree.  Core changes like this need to be run against as
many configs and previous gens as possible...

-- 
Jesse Barnes, Intel Open Source Technology Center

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Re: [PATCH 31/37] drm/i915: enable PCH earlier

[Eugeni Dodonov]

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On Wed, Mar 28, 2012 at 16:32, Jesse Barnes <jbarnes@virtuousgeek.org>wrote:

> On Thu, 22 Mar 2012 11:05:22 +0000
> Chris Wilson <chris@chris-wilson.co.uk> wrote:
>
> > On Wed, 21 Mar 2012 22:10:06 -0300, Eugeni Dodonov <
> eugeni.dodonov@intel.com> wrote:
> > > The modesetting sequence for PCH-related connections mentions that the
> > > order of plane/pipe enablement could happen either before of after PCH
> > > enablement.
> > >
> > > With LPT, however, we need to enable some things earlier to be able to
> > > talk to PCH. So let's do it a bit in advance.
> >
> > Touching modesetting sequence is a nerve racking experience. Can we
> > arrange to have this patch tested by itself, right now?
>
> Double plus agree.  Core changes like this need to be run against as
> many configs and previous gens as possible...
>

With the latest iteration of the patches, I managed to work-around this
properly. So I'll drop this patch from the next patch-bomb.

-- 
Eugeni Dodonov
<http://eugeni.dodonov.net/>

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