From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 14/18] drm/i915/context: switch contexts with execbuf2 Date: Thu, 29 Mar 2012 21:38:20 +0200 Message-ID: <20120329193820.GH27737@phenom.ffwll.local> References: <1332103198-25852-1-git-send-email-ben@bwidawsk.net> <1332103198-25852-15-git-send-email-ben@bwidawsk.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-we0-f177.google.com (mail-we0-f177.google.com [74.125.82.177]) by gabe.freedesktop.org (Postfix) with ESMTP id DB07F9E78C for ; Thu, 29 Mar 2012 12:37:37 -0700 (PDT) Received: by werp11 with SMTP id p11so1508018wer.36 for ; Thu, 29 Mar 2012 12:37:36 -0700 (PDT) In-Reply-To: <1332103198-25852-15-git-send-email-ben@bwidawsk.net> Content-Disposition: inline List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Ben Widawsky Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Sun, Mar 18, 2012 at 01:39:54PM -0700, Ben Widawsky wrote: > Use the rsvd1 field in execbuf2 to specify the context ID associated > with the workload. This will allow the driver to do the proper context > switch when/if needed. > > Signed-off-by: Ben Widawsky > --- > drivers/gpu/drm/i915/i915_gem_execbuffer.c | 6 ++++++ > include/drm/i915_drm.h | 4 +++- > 2 files changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c > index 81687af..c365e12 100644 > --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c > +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c > @@ -1058,6 +1058,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, > struct drm_i915_gem_object *batch_obj; > struct drm_clip_rect *cliprects = NULL; > struct intel_ring_buffer *ring; > + u32 ctx_id = args->context_info & I915_EXEC_CONTEXT_ID_MASK; > u32 exec_start, exec_len; > u32 seqno; > u32 mask; > @@ -1266,6 +1267,10 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, > goto err; > } > > + ret = i915_switch_context(ring, file, ctx_id, seqno, 0); > + if (ret) > + goto err; > + Already complained a bit about these: - Imo the seqno and hw_flags param can/should go away. - You need to add some sanity checks somewhere so that we correctly bail out of the do_execbuffer stuff without launching the batch. Obviously also a prime candidate for an i-g-t tests (because it'll nicely exercise a piece of code which usually is rather hard to tests). Aside: I haven't yet looked at your testcases, so maybe I'll come up with a crazy idea for another testcase ;-) > trace_i915_gem_ring_dispatch(ring, seqno); > > exec_start = batch_obj->gtt_offset + args->batch_start_offset; > @@ -1372,6 +1377,7 @@ i915_gem_execbuffer(struct drm_device *dev, void *data, > exec2.num_cliprects = args->num_cliprects; > exec2.cliprects_ptr = args->cliprects_ptr; > exec2.flags = I915_EXEC_RENDER; > + exec2.context_info = 0; > > ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); > if (!ret) { > diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h > index bead13e..03d159f 100644 > --- a/include/drm/i915_drm.h > +++ b/include/drm/i915_drm.h > @@ -660,13 +660,15 @@ struct drm_i915_gem_execbuffer2 { > #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) > #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ > __u64 flags; > - __u64 rsvd1; > + __u64 context_info; > __u64 rsvd2; > }; > > /** Resets the SO write offset registers for transform feedback on gen7. */ > #define I915_EXEC_GEN7_SOL_RESET (1<<8) > > +#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) > + > struct drm_i915_gem_pin { > /** Handle of the buffer to be pinned. */ > __u32 handle; > -- > 1.7.9.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Mail: daniel@ffwll.ch Mobile: +41 (0)79 365 57 48