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From: Daniel Vetter <daniel@ffwll.ch>
To: Jiri Slaby <jslaby@suse.cz>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>,
	LKML <linux-kernel@vger.kernel.org>,
	Jiri Slaby <jirislaby@gmail.com>,
	dri-devel@lists.freedesktop.org
Subject: Re: i915_driver_irq_handler: irq 42: nobody cared
Date: Tue, 10 Apr 2012 10:58:20 +0200	[thread overview]
Message-ID: <20120410085820.GC4115@phenom.ffwll.local> (raw)
In-Reply-To: <4F83F3B5.8080704@suse.cz>

On Tue, Apr 10, 2012 at 10:47:49AM +0200, Jiri Slaby wrote:
> On 04/09/2012 07:11 PM, Jesse Barnes wrote:
> > On Fri, 30 Mar 2012 11:45:43 +0100 Chris Wilson
> > <chris@chris-wilson.co.uk> wrote:
> > 
> >> On Fri, 30 Mar 2012 11:59:28 +0200, Jiri Slaby <jslaby@suse.cz>
> >> wrote:
> >>> I don't know what to dump more, because iir is obviously zero
> >>> too. What other sources of interrupts are on the (G33) chip?
> >> 
> >> IIR is the master interrupt, with chained secondary interrupt
> >> statuses. If IIR is 0, the interrupt wasn't raised by the GPU.
> > 
> > I've actually seen cases where one of the PIPE*STAT regs is stuck,
> > and even if IIR is 0 we still get interrupts... Jiri can you verify
> > the PIPE*STAT regs have bits set, maybe one or more we don't check
> > for?
> 
> Note that I already attached their contents... This is what is in them
> (pipes 0 and 1):
> [ 3572.968581] i915_driver_irq_handler: 0=00000000 1=00000000
> [ 3572.977472] i915_driver_irq_handler: 0=00000000 1=00000000
> [ 3576.224839] i915_driver_irq_handler: 0=00000000 1=00000000
> [ 3576.243558] i915_driver_irq_handler: 0=00000000 1=00000000
> [ 3576.384912] i915_driver_irq_handler: 0=00000000 1=00000000
> [ 3576.403462] i915_driver_irq_handler: 0=00000000 1=00000000
> [ 3577.464100] i915_driver_irq_handler: 0=00000000 1=00000000
> [ 3577.477383] i915_driver_irq_handler: 0=00000000 1=00000000
> [ 3577.829016] i915_driver_irq_handler: 0=00020000 1=00000000
> [ 3577.830093] i915_driver_irq_handler: 0=00020000 1=00000000
> 
> I.e. the handler is called when IIR=0 and both pipe stats are 0.

Hm, can you also dump the PORT_HOTPLUG_STAT register? That's the only
other subordinate interrupt source left.
-Daniel
-- 
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48

  reply	other threads:[~2012-04-10  8:57 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-03-27  8:40 i915_driver_irq_handler: irq 42: nobody cared Jiri Slaby
2012-03-27  8:42 ` Jiri Slaby
2012-03-30  9:59   ` Jiri Slaby
2012-03-30 10:45     ` Chris Wilson
2012-03-30 12:11       ` Jiri Slaby
2012-03-30 12:24         ` Chris Wilson
2012-04-06 21:31           ` i915_driver_irq_handler: irq 42: nobody cared [generic IRQ handling broken?] Jiri Slaby
2012-04-06 22:40             ` Thomas Gleixner
2012-04-09 17:12               ` Jesse Barnes
2012-04-09 17:52                 ` Dave Airlie
2012-04-10  8:44               ` Jiri Slaby
2012-04-10  8:50             ` Daniel Vetter
2012-04-10  8:52             ` i915_driver_irq_handler: irq 42: nobody cared Jiri Slaby
2012-04-10 16:50               ` Marcin Slusarz
2012-04-09 17:11       ` Jesse Barnes
2012-04-10  8:47         ` Jiri Slaby
2012-04-10  8:58           ` Daniel Vetter [this message]
2012-04-10  9:48             ` Jiri Slaby
2012-04-10 16:26           ` Jesse Barnes
2012-04-10 16:26             ` Jesse Barnes
2012-04-10 18:11             ` Jiri Slaby
2012-04-10 18:34               ` Jesse Barnes
2012-04-10 19:52                 ` Jiri Slaby
2012-04-10 20:32                   ` Daniel Vetter
2012-04-10 20:34                     ` Jesse Barnes
2012-04-10 20:34                       ` Jesse Barnes
2012-04-11 10:40                       ` Daniel Vetter
2012-05-03 19:56                         ` Jiri Slaby
2012-05-03 21:15                           ` Daniel Vetter
2012-05-03 21:15                             ` Daniel Vetter
2012-05-03 21:16                             ` Jiri Slaby
2012-05-03 21:54                               ` Jesse Barnes
2012-05-03 23:15                                 ` Ben Widawsky
2012-05-03 23:15                                   ` Ben Widawsky
2012-04-11  6:29                 ` Michel Dänzer
2012-04-11  6:29                   ` Michel Dänzer
2012-04-11 16:03                   ` Jesse Barnes
2012-03-27  8:57 ` Daniel Vetter
2012-03-27 10:54   ` Jiri Slaby

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