Re: [PATCH 4/7] drm/i915: properly set ppgtt cacheability on snb

[Ben Widawsky <ben@bwidawsk.net>]

On Sat, Mar 31, 2012 at 11:22:00AM +0200, Daniel Vetter wrote:
> For some reason snb has 2 fields to set ppgtt cacheability. This one
> here does not exist on gen7.
> 
> This might explain why ppgtt wasn't a win on snb like on ivb - not
> enough pte caching.

So, is it a win now?


> 
> Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
>  drivers/gpu/drm/i915/i915_gem.c |    3 +++
>  drivers/gpu/drm/i915/i915_reg.h |    4 ++++
>  2 files changed, 7 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 5dc5f42..cab70ef 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -3766,6 +3766,9 @@ void i915_gem_init_ppgtt(struct drm_device *dev)
>  	if (INTEL_INFO(dev)->gen == 6) {
>  		uint32_t ecochk, gab_ctl, ecobits;
>  
> +		ecobits = I915_READ(GAC_ECO_BITS); 
> +		I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
> +
>  		gab_ctl = I915_READ(GAB_CTL);
>  		I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
>  

Is this a bad rebase? This doesn't apply to whatever I am using.

> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e72c251..5457980 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -125,6 +125,10 @@
>  #define   ECOCHK_PPGTT_CACHE64B		(0x3<<3)
>  #define   ECOCHK_PPGTT_CACHE4B		(0x0<<3)
>  
> +#define GAC_ECO_BITS			0x14090
> +#define   ECOBITS_PPGTT_CACHE64B	(3<<8)
> +#define   ECOBITS_PPGTT_CACHE4B		(0<<8)
> +
>  #define GAB_CTL				0x24000
>  #define   GAB_CTL_CONT_AFTER_PAGEFAULT	(1<<8)
>  

According to bspec, but 13 must be set to a 1 also.