From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Tue, 17 Apr 2012 22:45:50 +0200 Subject: [U-Boot] [PATCH v2] Add support for MINI2440 (s3c2440). Documentation about the product can be found on: http://www.friendlyarm.net/products/mini2440 In-Reply-To: <1334694802-4881-1-git-send-email-contact@huau-gabriel.fr> References: <20120417200819.GA2975@debian> <1334694802-4881-1-git-send-email-contact@huau-gabriel.fr> Message-ID: <201204172245.50173.marex@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Dear Gabriel Huau, > --- > Changes for v2: > - Coding style cleanup > - Remove unnecessary files modification > - Remove unnecessary board configuration set > --- > arch/arm/include/asm/arch-s3c24x0/s3c24x0.h | 51 +----- > board/friendlyarm/mini2440/Makefile | 45 +++++ > board/friendlyarm/mini2440/lowlevel_init.S | 177 +++++++++++++++++ > board/friendlyarm/mini2440/mini2440.c | 283 > +++++++++++++++++++++++++++ boards.cfg | > 1 + > include/configs/mini2440.h | 203 +++++++++++++++++++ > 6 files changed, 710 insertions(+), 50 deletions(-) > create mode 100644 board/friendlyarm/mini2440/Makefile > create mode 100644 board/friendlyarm/mini2440/lowlevel_init.S > create mode 100644 board/friendlyarm/mini2440/mini2440.c > create mode 100644 include/configs/mini2440.h > > diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h > b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h index ca978c9..96e623b > 100644 > --- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h > +++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h > @@ -416,7 +416,7 @@ struct s3c24x0_gpio { > u32 misccr; > u32 extint; > #endif > -#ifdef CONFIG_S3C2410 > +#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) > u32 gpacon; > u32 gpadat; > u32 res1[2]; > @@ -467,55 +467,6 @@ struct s3c24x0_gpio { > u32 gstatus4; > #endif > #if defined(CONFIG_S3C2440) > - u32 gpacon; > - u32 gpadat; > - u32 res1[2]; > - u32 gpbcon; > - u32 gpbdat; > - u32 gpbup; > - u32 res2; > - u32 gpccon; > - u32 gpcdat; > - u32 gpcup; > - u32 res3; > - u32 gpdcon; > - u32 gpddat; > - u32 gpdup; > - u32 res4; > - u32 gpecon; > - u32 gpedat; > - u32 gpeup; > - u32 res5; > - u32 gpfcon; > - u32 gpfdat; > - u32 gpfup; > - u32 res6; > - u32 gpgcon; > - u32 gpgdat; > - u32 gpgup; > - u32 res7; > - u32 gphcon; > - u32 gphdat; > - u32 gphup; > - u32 res8; > - > - u32 misccr; > - u32 dclkcon; > - u32 extint0; > - u32 extint1; > - u32 extint2; > - u32 eintflt0; > - u32 eintflt1; > - u32 eintflt2; > - u32 eintflt3; > - u32 eintmask; > - u32 eintpend; > - u32 gstatus0; > - u32 gstatus1; > - u32 gstatus2; > - u32 gstatus3; > - u32 gstatus4; > - Why did you drop this? Also, put this in a separate patch please ... > u32 res9; > u32 dsc0; > u32 dsc1; > diff --git a/board/friendlyarm/mini2440/Makefile > b/board/friendlyarm/mini2440/Makefile new file mode 100644 > index 0000000..065f1db > --- /dev/null > +++ b/board/friendlyarm/mini2440/Makefile > @@ -0,0 +1,45 @@ > +# > +# (C) Copyright 2000-2006 2012 ;-) > +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. > +# > +# See file CREDITS for list of people who contributed to this > +# project. > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License, or (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with this program; if not, write to the Free Software > +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, > +# MA 02111-1307 USA > +# > + > +include $(TOPDIR)/config.mk > + > +LIB = $(obj)lib$(BOARD).o > + > +COBJS := mini2440.o > +SOBJS := lowlevel_init.o > + > +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) > +OBJS := $(addprefix $(obj),$(COBJS)) > +SOBJS := $(addprefix $(obj),$(SOBJS)) > + > +$(LIB): $(obj).depend $(OBJS) $(SOBJS) > + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) > + > +######################################################################### > + > +# defines $(obj).depend target > +include $(SRCTREE)/rules.mk > + > +sinclude $(obj).depend > + > +######################################################################### > diff --git a/board/friendlyarm/mini2440/lowlevel_init.S > b/board/friendlyarm/mini2440/lowlevel_init.S new file mode 100644 > index 0000000..2a057ea > --- /dev/null > +++ b/board/friendlyarm/mini2440/lowlevel_init.S > @@ -0,0 +1,177 @@ > +/* > + * Memory Setup stuff - taken from blob memsetup.S > + * > + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw at its.tudelft.nl) and > + * Jan-Derk Bakker (J.D.Bakker at its.tudelft.nl) > + * > + * Modified for the Samsung SMDK2410 by > + * (C) Copyright 2002 > + * David Mueller, ELSOFT AG, Your name is missing > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#include > +#include > + > +/* > + * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S > + * Copyright (C) 2002 Samsung Electronics SW.LEE > + */ > + > +#define BWSCON 0x48000000 > +#define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ > +#define INTSUBMSK 0x4A00001C > + > +/* BWSCON */ > +#define DW8 (0x0) > +#define DW16 (0x1) > +#define DW32 (0x2) > +#define WAIT (0x1<<2) > +#define UBLB (0x1<<3) > + > +#define B1_BWSCON (DW32) > +#define B2_BWSCON (DW16) > +#define B3_BWSCON (DW16 + WAIT + UBLB) > +#define B4_BWSCON (DW16 + WAIT + UBLB) > +#define B5_BWSCON (DW16) > +#define B6_BWSCON (DW32) > +#define B7_BWSCON (DW32) > + > +/* BANK0CON */ > +#define B0_Tacs 0x0 /* 0clk */ > +#define B0_Tcos 0x0 /* 0clk */ > +#define B0_Tacc 0x7 /* 14clk */ > +#define B0_Tcoh 0x0 /* 0clk */ > +#define B0_Tah 0x0 /* 0clk */ > +#define B0_Tacp 0x0 > +#define B0_PMC 0x0 /* normal */ > + > +/* BANK1CON */ > +#define B1_Tacs 0x0 /* 0clk */ > +#define B1_Tcos 0x0 /* 0clk */ > +#define B1_Tacc 0x7 /* 14clk */ > +#define B1_Tcoh 0x0 /* 0clk */ > +#define B1_Tah 0x0 /* 0clk */ > +#define B1_Tacp 0x0 > +#define B1_PMC 0x0 > + > +#define B2_Tacs 0x0 > +#define B2_Tcos 0x0 > +#define B2_Tacc 0x7 > +#define B2_Tcoh 0x0 > +#define B2_Tah 0x0 > +#define B2_Tacp 0x0 > +#define B2_PMC 0x0 > + > +#define B3_Tacs 0x0 /* 0clk */ > +#define B3_Tcos 0x3 /* 4clk */ > +#define B3_Tacc 0x7 /* 14clk */ > +#define B3_Tcoh 0x1 /* 1clk */ > +#define B3_Tah 0x3 /* 4clk */ > +#define B3_Tacp 0x0 /* 2clk */ > +#define B3_PMC 0x0 /* normal */ > + > +#define B4_Tacs 0x0 > +#define B4_Tcos 0x3 > +#define B4_Tacc 0x7 > +#define B4_Tcoh 0x1 > +#define B4_Tah 0x3 > +#define B4_Tacp 0x0 > +#define B4_PMC 0x0 > + > +#define B5_Tacs 0x0 /* 0clk */ > +#define B5_Tcos 0x0 /* 0clk */ > +#define B5_Tacc 0x7 /* 14clk */ > +#define B5_Tcoh 0x0 /* 0clk */ > +#define B5_Tah 0x0 /* 0clk */ > +#define B5_Tacp 0x0 > +#define B5_PMC 0x0 /* normal */ > + > +#define SDRAM_MT 0x3 /* SDRAM */ > +#define SDRAM_Trcd 0x0 /* 2clk */ > +#define SDRAM_SCAN_9 0x1 /* 9bit */ > +#define SDRAM_SCAN_10 0x2 /* 10bit */ > + > +#define SDRAM_128MB ((SDRAM_MT<<15)+(SDRAM_Trcd<<2)+(SDRAM_SCAN_10)) > +#define SDRAM_64MB ((SDRAM_MT<<15)+(SDRAM_Trcd<<2)+(SDRAM_SCAN_9)) > + > +/* REFRESH parameter */ > +#define REFEN 0x1 /* Refresh enable */ > +#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ > +#define Trp 0x1 /* 3clk */ > +#define Trc 0x3 /* 7clk */ > +#define Tchr 0x0 /* unused */ > + > +#define REFCNT 1012 /* period=10.37us, HCLK=100Mhz, (2048+1-10.37*100) Either move this to header or make this start.S generic. > */ + > +_TEXT_BASE: > + .word CONFIG_SYS_TEXT_BASE > + > +.globl lowlevel_init > +lowlevel_init: > + // disable all interupts The gas can crunch such c++ comments? > + mov r1, #0xffffffff > + ldr r0, =INTMSK > + str r1, [r0] > + > + ldr r1, =0x7fff > + ldr r0, =INTSUBMSK > + str r1, [r0] > + > + /* memory control configuration */ > + /* make r0 relative the current location so that it */ > + /* reads SMRDATA out of FLASH rather than memory ! */ > + ldr r0, =SMRDATA > + ldr r1, _TEXT_BASE > + sub r0, r0, r1 > + ldr r1, =BWSCON /* Bus Width Status Controller */ > + add r2, r0, #13*4 > +0: > + ldr r3, [r0], #4 > + str r3, [r1], #4 > + cmp r2, r0 > + bne 0b > + > + /* > + * SDRAM configuration for 64MB > + */ > + ldr r1, =BWSCON+(7*4) > + ldr r0, =SDRAM_64MB > + str r0, [r1], #4 > + str r0, [r1] > +return: > + /* everything is fine now */ > + mov pc, lr > + > + .ltorg > +SMRDATA: > + .word > (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCO > N<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) + .word > ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tac > p<<2)+(B0_PMC)) + .word > ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tac > p<<2)+(B1_PMC)) + .word > ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tac > p<<2)+(B2_PMC)) + .word > ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tac > p<<2)+(B3_PMC)) + .word > ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tac > p<<2)+(B4_PMC)) + .word > ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tac > p<<2)+(B5_PMC)) + .word SDRAM_128MB > + .word SDRAM_128MB SDRAM128? You had SDRAM64 there before ... > + .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) > + .word 0xb2 /* enable burst */ > + .word 0x30 > + .word 0x30 > diff --git a/board/friendlyarm/mini2440/mini2440.c > b/board/friendlyarm/mini2440/mini2440.c new file mode 100644 > index 0000000..ecfb519 > --- /dev/null > +++ b/board/friendlyarm/mini2440/mini2440.c > @@ -0,0 +1,283 @@ > +/* > + * (C) Copyright 2002 > + * Sysgo Real-Time Solutions, GmbH > + * Marius Groeger > + * > + * (C) Copyright 2002 > + * David Mueller, ELSOFT AG, > + * > + * (C) Copyright 2009 > + * Michel Pollet > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#include > +#include > +#include > + > +#ifdef CONFIG_DRIVER_DM9000 > +#include > +#endif > + > +DECLARE_GLOBAL_DATA_PTR; > + > +/* FCLK = 405 MHz, HCLK = 101 MHz, PCLK = 50 MHz, UCLK = 48 MHz */ > +#define CLKDIVN_VAL 7 > +#define M_MDIV 0x7f > +#define M_PDIV 0x2 > +#define M_SDIV 0x1 > + > +#define U_M_MDIV 0x38 > +#define U_M_PDIV 0x2 > +#define U_M_SDIV 0x2 > + > +#define MVAL (0) > +#define MVAL_USED (0) //0=each frame 1=rate by MVAL > +#define INVVDEN (1) //0=normal 1=inverted > +#define BSWP (0) //Byte swap control > +#define HWSWP (1) //Half word swap control C++ comments, move this stuff to separate define too ? > + > +//TFT 240320 > +#define LCD_XSIZE_TFT_240320 (240) > +#define LCD_YSIZE_TFT_240320 (320) > + > +//TFT240320 > +#define HOZVAL_TFT_240320 (LCD_XSIZE_TFT_240320-1) > +#define LINEVAL_TFT_240320 (LCD_YSIZE_TFT_240320-1) > + > +//Timing parameter for NEC3.5" > +#define VBPD_240320 (3) > +#define VFPD_240320 (10) > +#define VSPW_240320 (1) > + > +#define HBPD_240320 (5) > +#define HFPD_240320 (2) > +#define HSPW_240320 (36) > + > +#define CLKVAL_TFT_240320 (3) > + > +static inline void delay (unsigned long loops) > +{ > + __asm__ volatile ("1:\n" > + "subs %0, %1, #1\n" > + "bne 1b":"=r" (loops):"0" (loops)); Why do you need this? > +} > + > +int arch_cpu_init (void) > +{ > + struct s3c24x0_clock_power * const clk_power = > s3c24x0_get_base_clock_power(); + int i; > + > + /* to reduce PLL lock time, adjust the LOCKTIME register */ > + clk_power->locktime = 0xFFFFFF; > + clk_power->clkdivn = CLKDIVN_VAL; > + > + /* configure UPLL */ > + clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); > + /* some delay between MPLL and UPLL */ > + for(i = 0; i < 100000; i++); This will be opt-out by GCC under certain conditions, unless you put membarrier here ... which is not what you want to do -- just add simple udelay() here ? > + > + /* configure MPLL */ > + clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); > + > + /* some delay between MPLL and UPLL */ > + for(i = 0; i < 500000; i++); > + > + return 0; > +} > + > +/* > + * Miscellaneous platform dependent initialisations > + */ > +int board_init (void) > +{ > + struct s3c24x0_clock_power * const clk_power = > s3c24x0_get_base_clock_power(); + struct s3c24x0_gpio * const gpio = > s3c24x0_get_base_gpio(); > + > + /* to reduce PLL lock time, adjust the LOCKTIME register */ > + clk_power->locktime = 0xFFFFFF; > + clk_power->clkdivn = CLKDIVN_VAL; > + > + /* configure UPLL */ > + clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); > + /* some delay between MPLL and UPLL */ > + delay (10); > + /* configure MPLL */ > + clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); > + > + /* some delay between MPLL and UPLL */ > + delay (8000); > + > + gpio->gpacon = 0x007FFFFF; /* Port A is all "special" */ > + // port B outputs reconfigured > + gpio->gpbcon = > + (0x1 << 0) | // GPB0 OUT TOUT0 PWM Buzzer > + (0x2 << 2) | // GPB1 OUT TOUT1 LCD Backlight > + (0x1 << 4) | // GPB2 OUT L3MODE > + (0x1 << 6) | // GBP3 OUT L3DATA > + (0x1 << 8) | // GBP4 OUT L3CLOCK > + (0x1 << 10) | // GBP5 OUT LED1 > + (0x1 << 12) | // GBP6 OUT LED2 > + (0x1 << 14) | // GBP7 OUT LED3 > + (0x1 << 16) | // GBP8 OUT LED4 > + (0x2 << 18) | // GBP9 --- nXDACK0 CON5 EBI > + (0x2 << 20) | // GBP10 --- nXDREQ0 CON5 EBI > + 0; > + gpio->gpbup = (1 << 10) - 1; // disable pullup on all 10 pins > + gpio->gpbdat = > + (0 << 5) | /* turn LED 1 on */ > + (1 << 6) | /* turn LED 1 off */ > + (1 << 7) | /* turn LED 1 off */ > + (1 << 8) | /* turn LED 1 off */ > + 0; > + > + // lcd signals on C and D Did you run this through ./tools/checkpatch.pl ? > + gpio->gpccon = (0xAAAAAAAA & /* all default IN but ... */ > + ~(0x3 << 10)) | /* not pin 5 ... */ > + (0x1 << 10); /* that is output (USBD) */ > + gpio->gpcup = 0xFFFFFFFF; > + gpio->gpcdat = 0; > + > + gpio->gpdcon = 0xAAAAAAAA; > + gpio->gpdup = 0xFFFFFFFF; > + // port E is set for all it's special functions (i2c, spi etc) > + gpio->gpecon = 0xAAAAAAAA; > + gpio->gpeup = 0x0000FFFF; > + > + gpio->gpfcon = > + (0x1 << 0) | // GPG0 EINT0 OUT > + (0x1 << 2) | // GPG1 EINT1 OUT > + (0x1 << 4) | // GPG2 EINT2 OUT > + (0x1 << 6) | // GPG3 EINT3 OUT > + (0x1 << 8) | // GPG4 EINT4 OUT > + (0x1 << 10) | // GPG5 EINT5 OUT > + (0x1 << 12) | // GPG6 EINT6 OUT > + (0x0 << 14) | // GPG7 EINT7 IN DM9000 > + 0; > + gpio->gpfdat = 0; > + gpio->gpfup = > + ((1 << 7) - 1) // all disabled > + & ~( 1 << 7 ) // but for the ethernet one, we need it. > + ; Friendship is magic, that's true ... but magic doesn't make good friendship ;-D > + gpio->gpgcon = > + (0x0 << 0) | // GPG0 EINT8 IN Key1 > + (0x1 << 2) | // GPG1 EINT9 OUT Con5 > + (0x1 << 4) | // GPG2 EINT10 OUT > + (0x0 << 6) | // GPG3 EINT11 IN Key2 > + (0x0 << 8) | // GPG4 EINT12 IN Smart Screen Interrupt > + (0x0 << 10) | // GPG5 EINT13 IN Key3 > + (0x0 << 12) | // GPG6 EINT14 IN Key4 > + (0x0 << 14) | // GPG7 EINT15 IN Key5 > + (0x1 << 16) | // GPG8 EINT16 OUT nCD_SD > + (0x1 << 18) | // GPG9 EINT17 OUT > + (0x1 << 20) | // GPG10 EINT18 OUT > + (0x0 << 22) | // GPG11 EINT19 IN Key6 > + (0x0 << 24) | // GPG12 EINT18 IN // GPG[12..15] need to be inputs > + (0x0 << 26) | // GPG13 EINT18 IN // hard pullups > + (0x0 << 28) | // GPG14 EINT18 IN > + (0x0 << 30) | // GPG15 EINT18 IN > + 0; > + gpio->gpgup = (1 << 15) -1; // disable pullups for all pins > + > + gpio->gphcon = > + (0x2 << 0) | // GPH0 nCTS0 --- > + (0x2 << 2) | // GPH1 nRTS0 --- > + (0x2 << 4) | // GPH2 TXD0 --- > + (0x2 << 6) | // GPH3 RXD0 --- > + (0x2 << 8) | // GPH4 TXD1 --- > + (0x2 << 10) | // GPH5 RXD1 --- > + (0x2 << 12) | // GPH6 [TXD2] nRTS1 > + (0x2 << 14) | // GPH7 [RXD2] nCTS1 > + (0x1 << 16) | // GPH8 UEXTCLK OUT > + (0x1 << 18) | // GPH9 CLKOUT0 OUT > + (0x1 << 20) | // GPH10 CLKOUT1 OUT > + 0; > + gpio->gphup = (1 << 10) - 1; // disable pullups for all pins > + > + gpio->extint0=0x22222222; > + gpio->extint1=0x22222222; > + gpio->extint2=0x22222222; > + > + /* USB Device Part */ > + /* GPC5 is reset for USB Device */ > + gpio->gpcdat |= ( 1 << 5) ; > + udelay(20000); > + gpio->gpcdat &= ~( 1 << 5) ; > + udelay(20000); > + gpio->gpcdat |= ( 1 << 5) ; Drop the magic bloat, replace with #defined stuff in header files. > + > + /* arch number from kernel post 2.6.28 */ > +#ifndef MACH_TYPE_MINI2440 > +#define MACH_TYPE_MINI2440 1999 > +#endif #define MACH_TYPE ... see eg. include/configs/m28evk.h and arch/arm/lib/board.c, you can drop it all. > + gd->bd->bi_arch_number = MACH_TYPE_MINI2440; > + > + /* adress of boot parameters */ > + gd->bd->bi_boot_params = 0x30000100; > + > + return 0; > +} > + > +void board_video_init(GraphicDevice *pGD) > +{ > + struct s3c24x0_lcd * const lcd = s3c24x0_get_base_lcd(); > + > + /* FIXME: select LCM type by env variable */ > + /* Configuration for GTA01 LCM on QT2410 */ > + lcd->lcdcon1 = 0x00000378; /* CLKVAL=4, BPPMODE=16bpp, TFT, ENVID=0 */ > + lcd->lcdcon5 = 0x00000f09; > + > + lcd->lcdcon2 = > (VBPD_240320<<24)|(LINEVAL_TFT_240320<<14)|(VFPD_240320<<6)|(VSPW_240320); > + lcd->lcdcon3 = (HBPD_240320<<19)|(HOZVAL_TFT_240320<<8)|(HFPD_240320); > + lcd->lcdcon4 = (MVAL<<8)|(HSPW_240320); > + > + lcd->lpcsel = 0x00000000; > +} > + > +void dram_init_banksize (void) > +{ > + struct s3c24x0_memctl * const mem = s3c24x0_get_base_memctl(); > + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; > + /* if the early bootloader found 128MB, lets tell the kernel */ > + if ((mem->bankcon[6] & 0x3) == 0x2) > + gd->bd->bi_dram[0].size = 128*1024*1024; > + else > + gd->bd->bi_dram[0].size = 64*1024*1024; Magic bloat, fix. > +} > + > +int dram_init (void) > +{ > + gd->ram_size = 64*1024*1024; > + return 0; > +} > + > +int board_eth_init(bd_t *bis) > +{ > +#ifdef CONFIG_DRIVER_DM9000 > + return dm9000_initialize(bis); > +#else > + return 0; > +#endif > +} > + > +/* The sum of all part_size[]s must equal to the NAND size, i.e., > 0x4000000 */ +unsigned int dynpart_size[] = { 0x40000, 0x20000, 0x500000, > 0xffffffff, 0 }; +char *dynpart_names[] = { "u-boot", "u-boot_env", > "kernel", "rootfs", NULL }; diff --git a/boards.cfg b/boards.cfg > index 3cf75c3..93eeb3c 100644 > --- a/boards.cfg > +++ b/boards.cfg > @@ -61,6 +61,7 @@ mx1ads arm arm920t - > - scb9328 arm arm920t - > - imx cm4008 arm > arm920t - - ks8695 cm41xx > arm arm920t - - ks8695 > +mini2440 arm arm920t mini2440 > friendlyarm s3c24x0 VCMA9 arm arm920t > vcma9 mpl s3c24x0 smdk2410 > arm arm920t - samsung s3c24x0 > omap1510inn arm arm925t - > ti diff --git a/include/configs/mini2440.h b/include/configs/mini2440.h > new file mode 100644 > index 0000000..8b04a76 > --- /dev/null > +++ b/include/configs/mini2440.h > @@ -0,0 +1,203 @@ > +/* > + * (C) Copyright 2002 > + * Sysgo Real-Time Solutions, GmbH > + * Marius Groeger > + * Gary Jennejohn > + * David Mueller > + * > + * (C) Copyright 2009-2010 > + * Michel Pollet > + * > + * (C) Copyright 2012 > + * Gabriel Huau > + * > + * Configuation settings for the MINI2440 board. > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#ifndef __CONFIG_H > +#define __CONFIG_H > + > +#define CONFIG_SYS_TEXT_BASE 0x0 > + > +/* > + * High Level Configuration Options > + */ > +#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ > +#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C2440 SoC */ > +#define CONFIG_S3C2440 1 /* in a SAMSUNG S3C2440 SoC Indent here is inconsistent! > */ > +#define CONFIG_MINI2440 1 /* on a MIN2440 Board */ > + > +/* > + * It is possible to have u-boot save it's environment in NOR, however, > + * reember it is incompatible with booting from NAND as the NOR is not > + * available at that point. So use this only if you use nand as storage > + * and will never boot from it > + */ > +#define CONFIG_MINI2440_NOR_ENV 1 > +#define CONFIG_MINI2440_OVERCLOCK 1 /* allow use of frequencies over > 405Mhz */ + > +/* > + * input clock of PLL > + */ > +#define CONFIG_SYS_CLK_FREQ 12000000 /* MINI2440 has 12.0000MHz input > clock */ +#define CONFIG_ARCH_CPU_INIT 1 /* for the initialization of PLL > */ + > +#define USE_920T_MMU 1 > +#define CONFIG_BAUDRATE 115200 > + > +/* > + * Size of malloc() pool > + */ > +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024) > +#define CONFIG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial > data */ + > +/* > + * Hardware drivers > + */ > +#define CONFIG_DRIVER_DM9000 1 > +#define CONFIG_DRIVER_DM9000_NO_EEPROM 1 > +#define CONFIG_DM9000_BASE 0x20000300 > +#define DM9000_IO CONFIG_DM9000_BASE > +#define DM9000_DATA (CONFIG_DM9000_BASE+4) > + > +/* > + * select serial console configuration > + */ > +#define CONFIG_S3C24X0_SERIAL > +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on MINI2440 */ > + > +/* > + * allow to overwrite serial and ethaddr > + */ > +#define CONFIG_ENV_OVERWRITE > + > +/* > + * Command definition > + */ > +#include > + > +#define CONFIG_CMD_DHCP > +#define CONFIG_CMD_PORTIO > +#define CONFIG_CMD_REGINFO > +#define CONFIG_CMD_SAVES > + > +/* > + * Miscellaneous configurable options > + */ > +#define CONFIG_LONGHELP /* undef to save memory */ > +#define CONFIG_SYS_PROMPT "MINI2440 # " /* Monitor Make this "=> " > Command Prompt */ > +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ > +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) > /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 32 /* max number of > command args */ > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer > Size */ + > +#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ > +#define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64 MB in DRAM */ > + > +#undef CONFIG_CLKS_IN_HZ /* everything, incl board info, in Hz */ > + > +#define CONFIG_SYS_LOAD_ADDR 0x32000000 /* default load address */ > + > +/* > + * the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need > + * it to wrap 100 times (total 1562500) to get 1 sec. > + */ > +#define CONFIG_SYS_HZ 1562500 > + > +/* > + * valid baudrates > + */ > +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } > + > +/* > + * Stack sizes > + * The stack sizes are set up in start.S using the settings below > + */ > +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ > +#ifdef CONFIG_USE_IRQ > +#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */ > +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ > +#endif > + > +/* > + * Physical Memory Map > + */ > +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM > */ +#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ > +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 > +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100000 - \ > + GENERATED_GBL_DATA_SIZE) > + > +/* > + * When booting from NAND, it is impossible to access the lowest addresses > + * due to the SteppingStone being in the way. Luckily the NOR doesn't > really + * care about the highest 16 bits of address, so we set the > controlers + * registers to go and poke over there, instead. > + */ > +#define PHYS_FLASH_1 0x0 > +#define CONFIG_SYS_FLASH_BASE 0x0 > + > +/* > + * NOR FLASH organization > + * Now uses the standard CFI interface > + * FLASH and environment organization > + */ > +#define CONFIG_SYS_FLASH_CFI 1 > +#define CONFIG_FLASH_CFI_DRIVER 1 > +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT > +#define CONFIG_SYS_MONITOR_BASE 0x0 > +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ > +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 512 * 4096 sectors, or 32 * 64k > blocks */ +#define CONFIG_FLASH_SHOW_PROGRESS 1 > + > +/* > + * u-boot environmnent > + */ > +#define CONFIG_BOOTDELAY 3 > +#define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 > console=ttySAC0,115200" +#define CONFIG_ETHADDR 08:08:11:18:12:27 > +#define CONFIG_NETMASK 255.255.255.0 > +#define CONFIG_IPADDR 192.168.0.2 > +#define CONFIG_SERVERIP 192.168.0.1 Remove, NAK. > +#define CONFIG_DOS_PARTITION 1 > +#define CONFIG_BOOTCOMMAND "tftp 0x32000000 uImage;setenv bootargs > console=ttySAC0,115200 mem=16M noinitrd mini2440=5tb ip=dhcp;bootm" + > +#ifndef CONFIG_MINI2440_NOR_ENV > + #define CONFIG_ENV_IS_IN_NAND 1 > + #define CONFIG_ENV_OFFSET_OOB 1 // dont define for CONFIG_ENV_IS_IN_FLASH > + /* This size must be the size of a common denominator for the NAND erase > block */ + #define CONFIG_ENV_SIZE 0x20000 /* 128k Total Size of > Environment Sector */ +#else > + #define CONFIG_ENV_IS_IN_FLASH 1 > + #define CONFIG_MY_ENV_OFFSET 0x40000 > + #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_MY_ENV_OFFSET) /* addr of > environment */ + #define CONFIG_ENV_SIZE 0x4000 /* 16k Total Size of > Environment Sector */ +#endif > +#define CONFIG_PREBOOT_OVERRIDE 1 > + > +/* ATAG configuration */ > +#define CONFIG_INITRD_TAG 1 > +#define CONFIG_SETUP_MEMORY_TAGS 1 > +#define CONFIG_CMDLINE_TAG 1 > +#define CONFIG_CMDLINE_EDITING 1 > +#define CONFIG_AUTO_COMPLETE 1 > + > +#endif /* __CONFIG_H */