From: Daniel Vetter <daniel@ffwll.ch>
To: Eugeni Dodonov <eugeni.dodonov@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 01/24] drm/i915: add Haswell DIP controls registers
Date: Thu, 26 Apr 2012 21:18:52 +0200 [thread overview]
Message-ID: <20120426191852.GI5156@phenom.ffwll.local> (raw)
In-Reply-To: <1335464479-648-2-git-send-email-eugeni.dodonov@intel.com>
On Thu, Apr 26, 2012 at 03:20:56PM -0300, Eugeni Dodonov wrote:
> Haswell has different DIP control registers and offsets.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Afaict hsw has a dip reg for every type of info frame, whereas older
machines have one dip reg and a switch in the control reg. Can you please
the definitions for the other regs here, too, and a big yelling FIXME
comment in the second patch saying that this is a hack and Paulo needs to
fix things up?
-Daniel
> ---
> drivers/gpu/drm/i915/i915_reg.h | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f1f4d8f..4f17b74 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3518,6 +3518,22 @@
> #define VLV_TVIDEO_DIP_GCP(pipe) \
> _PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
>
> +/* Haswell DIP controls */
> +#define HSW_VIDEO_DIP_CTL_A 0x60200
> +#define HSW_VIDEO_DIP_AVI_DATA_A 0x60220
> +#define HSW_VIDEO_DIP_GCP_A 0x60210
> +
> +#define HSW_VIDEO_DIP_CTL_B 0x61200
> +#define HSW_VIDEO_DIP_AVI_DATA_B 0x61220
> +#define HSW_VIDEO_DIP_GCP_B 0x61210
> +
> +#define HSW_TVIDEO_DIP_CTL(pipe) \
> + _PIPE(pipe, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B)
> +#define HSW_TVIDEO_DIP_AVI_DATA(pipe) \
> + _PIPE(pipe, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B)
> +#define HSW_TVIDEO_DIP_GCP(pipe) \
> + _PIPE(pipe, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B)
> +
> #define _TRANS_HTOTAL_B 0xe1000
> #define _TRANS_HBLANK_B 0xe1004
> #define _TRANS_HSYNC_B 0xe1008
> --
> 1.7.10
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Mail: daniel@ffwll.ch
Mobile: +41 (0)79 365 57 48
next prev parent reply other threads:[~2012-04-26 19:17 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-04-26 18:20 [PATCH 00/24] Haswell v4 Eugeni Dodonov
2012-04-26 18:20 ` [PATCH 01/24] drm/i915: add Haswell DIP controls registers Eugeni Dodonov
2012-04-26 19:18 ` Daniel Vetter [this message]
2012-04-30 23:46 ` Jesse Barnes
2012-04-26 18:20 ` [PATCH 02/24] drm/i915: support infoframes on Haswell Eugeni Dodonov
2012-04-26 18:20 ` [PATCH 03/24] drm/i915: add support for SBI ops Eugeni Dodonov
2012-04-30 23:53 ` Jesse Barnes
2012-04-26 18:20 ` [PATCH 04/24] drm/i915: calculate same watermarks on Haswell as on Ivy Bridge Eugeni Dodonov
2012-04-26 18:31 ` Jesse Barnes
2012-04-26 18:51 ` Eugeni Dodonov
2012-04-30 23:54 ` Jesse Barnes
2012-04-26 18:21 ` [PATCH 05/24] drm/i915: reuse Ivybridge interrupts code for Haswell Eugeni Dodonov
2012-04-30 23:55 ` Jesse Barnes
2012-04-26 18:21 ` [PATCH 06/24] drm/i915: properly check for pipe count Eugeni Dodonov
2012-04-30 23:57 ` Jesse Barnes
2012-04-26 18:21 ` [PATCH 07/24] drm/i915: show unknown sdvox registers on hdmi init Eugeni Dodonov
2012-04-30 23:58 ` Jesse Barnes
2012-04-26 18:21 ` [PATCH 08/24] drm/i915: do not use fdi_normal_train on haswell Eugeni Dodonov
2012-04-30 23:59 ` Jesse Barnes
2012-04-26 18:21 ` [PATCH 09/24] drm/i915: detect PCH encoders on Haswell Eugeni Dodonov
2012-05-01 0:00 ` Jesse Barnes
2012-04-26 18:21 ` [PATCH 10/24] drm/i915: enable power wells on haswell init Eugeni Dodonov
2012-05-01 0:05 ` Jesse Barnes
2012-04-26 18:21 ` [PATCH 11/24] drm/i915: program WM_LINETIME on Haswell Eugeni Dodonov
2012-05-01 0:05 ` Jesse Barnes
2012-04-26 18:21 ` [PATCH 12/24] drm/i915: add LPT PCH checks Eugeni Dodonov
2012-05-01 0:06 ` Jesse Barnes
2012-04-26 18:21 ` [PATCH 13/24] drm/i915: handle DDI-related assertions Eugeni Dodonov
2012-05-01 0:07 ` Jesse Barnes
2012-04-26 18:21 ` [PATCH 14/24] drm/i915: account for only one PCH receiver on Haswell Eugeni Dodonov
2012-04-26 19:54 ` Daniel Vetter
2012-05-01 0:09 ` Jesse Barnes
2012-04-26 18:21 ` [PATCH 15/24] drm/i915: initialize DDI buffer translations Eugeni Dodonov
2012-04-26 19:16 ` Eugeni Dodonov
2012-05-01 0:20 ` Jesse Barnes
2012-05-01 0:27 ` Eugeni Dodonov
2012-04-26 18:21 ` [PATCH 16/24] drm/i915: support DDI training in FDI mode Eugeni Dodonov
2012-04-26 19:43 ` Daniel Vetter
2012-04-26 18:21 ` [PATCH 17/24] drm/i915: disable pipe DDI function when disabling pipe Eugeni Dodonov
2012-05-01 0:23 ` Jesse Barnes
2012-04-26 18:21 ` [PATCH 18/24] drm/i915: program iCLKIP on Lynx Point Eugeni Dodonov
2012-05-01 0:26 ` Jesse Barnes
2012-04-26 18:21 ` [PATCH 19/24] drm/i915: detect digital outputs on Haswell Eugeni Dodonov
2012-05-01 0:27 ` Jesse Barnes
2012-05-01 0:33 ` Eugeni Dodonov
2012-05-01 15:01 ` Jesse Barnes
2012-05-02 3:02 ` Keith Packard
2012-04-26 18:21 ` [PATCH 20/24] drm/i915: add support for DDI-controlled digital outputs Eugeni Dodonov
2012-05-01 0:28 ` Jesse Barnes
2012-04-26 18:21 ` [PATCH 21/24] drm/i915: add WR PLL programming table Eugeni Dodonov
2012-04-26 18:21 ` [PATCH 22/24] drm/i915: move HDMI structs to shared location Eugeni Dodonov
2012-05-01 0:29 ` Jesse Barnes
2012-04-26 18:21 ` [PATCH 23/24] drm/i915: prepare HDMI link for Haswell Eugeni Dodonov
2012-04-26 18:21 ` [PATCH 24/24] drm/i915: hook Haswell devices in place Eugeni Dodonov
2012-04-26 19:33 ` [PATCH 01/24] drm/i915: add Haswell DIP controls registers Eugeni Dodonov
2012-04-26 19:33 ` [PATCH 02/24] drm/i915: support infoframes on Haswell Eugeni Dodonov
2012-04-26 19:42 ` [PATCH 01/24] drm/i915: add Haswell DIP controls registers Eugeni Dodonov
2012-04-30 23:50 ` Jesse Barnes
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