From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jesse Barnes Subject: Re: [PATCH 14/24] drm/i915: account for only one PCH receiver on Haswell Date: Mon, 30 Apr 2012 17:09:49 -0700 Message-ID: <20120430170949.563e23b9@jbarnes-desktop> References: <1335464479-648-1-git-send-email-eugeni.dodonov@intel.com> <1335464479-648-15-git-send-email-eugeni.dodonov@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from oproxy1-pub.bluehost.com (oproxy1-pub.bluehost.com [66.147.249.253]) by gabe.freedesktop.org (Postfix) with SMTP id 48F359EB4E for ; Mon, 30 Apr 2012 17:09:52 -0700 (PDT) In-Reply-To: <1335464479-648-15-git-send-email-eugeni.dodonov@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Eugeni Dodonov Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, 26 Apr 2012 15:21:09 -0300 Eugeni Dodonov wrote: > On Haswell, only one pipe can work in FDI mode, so this patch prevents > messing with wrong registers when FDI is being used by non-first pipe. > > Signed-off-by: Eugeni Dodonov > --- > drivers/gpu/drm/i915/intel_display.c | 19 ++++++++++++++++--- > 1 file changed, 16 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index b2d3dc1..6509402 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -978,9 +978,14 @@ static void assert_fdi_rx(struct drm_i915_private *dev_priv, > u32 val; > bool cur_state; > > - reg = FDI_RX_CTL(pipe); > - val = I915_READ(reg); > - cur_state = !!(val & FDI_RX_ENABLE); > + if (IS_HASWELL(dev_priv->dev) && pipe > 0) { > + DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n"); > + return; > + } else { > + reg = FDI_RX_CTL(pipe); > + val = I915_READ(reg); > + cur_state = !!(val & FDI_RX_ENABLE); > + } > WARN(cur_state != state, > "FDI RX state assertion failure (expected %s, current %s)\n", > state_string(state), state_string(cur_state)); > @@ -1013,6 +1018,10 @@ static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv, > int reg; > u32 val; > > + if (IS_HASWELL(dev_priv->dev) && pipe > 0) { > + DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n"); > + return; > + } > reg = FDI_RX_CTL(pipe); > val = I915_READ(reg); > WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n"); > @@ -1484,6 +1493,10 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv, > assert_fdi_tx_enabled(dev_priv, pipe); > assert_fdi_rx_enabled(dev_priv, pipe); > > + if (IS_HASWELL(dev_priv->dev) && pipe > 0) { > + DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n"); > + return; > + } > reg = TRANSCONF(pipe); > val = I915_READ(reg); > pipeconf_val = I915_READ(PIPECONF(pipe)); Yuck... good thing only VGA is on the PCH. If you don't end up doing separate high level functions for this: Reviewed-by: Jesse Barnes -- Jesse Barnes, Intel Open Source Technology Center