From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ben Widawsky <ben@bwidawsk.net>
Subject: Re: [PATCH] drm/i915: Wait for the clocks to stabilise
 before updating PLLs
Date: Wed, 2 May 2012 13:14:59 -0700
Message-ID: <20120502131459.0fdbb7b5@bwidawsk.net>
References: <1335987836-27149-1-git-send-email-chris@chris-wilson.co.uk>
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On Wed,  2 May 2012 20:43:56 +0100
Chris Wilson <chris@chris-wilson.co.uk> wrote:

> Cc: Ben Widawsky <ben@bwidawsk.net>
> Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Reported-and-tested-by: Ben Widawsky <ben@bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/intel_display.c |    7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d5aa2d2..b97112c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2845,11 +2845,14 @@ found:
>  	DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
>  prepare: /* separate function? */
>  	DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
> -	I915_WRITE(pll->fp0_reg, fp);
> -	I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
>  
> +	/* Wait for the clocks to stabilize before rewriting the regs */
> +	I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
>  	POSTING_READ(pll->pll_reg);
>  	udelay(150);
> +
> +	I915_WRITE(pll->fp0_reg, fp);
> +	I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
>  	pll->on = false;
>  	return pll;
>  }



-- 
Ben Widawsky, Intel Open Source Technology Center