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Date: Tue, 15 May 2012 16:04:57 +0200
From: Borislav Petkov <bp@amd64.org>
To: Steven Rostedt <rostedt@goodmis.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>, Luming Yu <luming.yu@gmail.com>,
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Subject: Re: [PATCH v5 6/7] x86/tlb: optimizing flush_tlb_mm
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On Tue, May 15, 2012 at 09:39:05AM -0400, Steven Rostedt wrote:
> > But you have to weight that against the cost of re-population, and
> > that's the difficult bit, since we have no clue how many tlb entries are
> > in use by the current cr3.
> > 
> > It might be possible for intel to give us this information, I've asked
> > for something similar for cachelines.
> 
> What information? The # of tlb entries in use?

... by the current %cr3, yes.

And also, before we delve into details, we still don't have a
representative benchmark where this shows any improvement.

-- 
Regards/Gruss,
Boris.

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