From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 2/7] drm/i915: Enable DP panel power sequencing for ValleyView Date: Wed, 13 Jun 2012 10:05:07 +0200 Message-ID: <20120613080507.GA4829@phenom.ffwll.local> References: <1339537655-5792-1-git-send-email-jbarnes@virtuousgeek.org> <1339537655-5792-3-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-wi0-f171.google.com (mail-wi0-f171.google.com [209.85.212.171]) by gabe.freedesktop.org (Postfix) with ESMTP id 46C189E9F7 for ; Wed, 13 Jun 2012 01:03:42 -0700 (PDT) Received: by wibhm14 with SMTP id hm14so3674254wib.12 for ; Wed, 13 Jun 2012 01:03:41 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1339537655-5792-3-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes Cc: Beeresh G , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Jun 12, 2012 at 02:47:30PM -0700, Jesse Barnes wrote: > From: Shobhit Kumar > > VLV supports two dp panels, there are two set of panel power sequence > registers which needed to be programmed based on the configured > pipe. This patch add supports for the same > > Acked-by: Acked-by: Ben Widawsky > Signed-off-by: Beeresh G > Reviewed-by: Vijay Purushothaman > Reviewed-by: Jesse Barnes > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++++++ > drivers/gpu/drm/i915/intel_dp.c | 8 +++++++- > 2 files changed, 19 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 281446d..a9e9d92 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3854,6 +3854,18 @@ > > #define BLC_PWM_PCH_CTL2 0xc8254 > > +#define PIPEA_PP_STATUS 0x61200 > +#define PIPEA_PP_CONTROL 0x61204 > +#define PIPEA_PP_ON_DELAYS 0x61208 > +#define PIPEA_PP_OFF_DELAYS 0x6120c > +#define PIPEA_PP_DIVISOR 0x61210 > + > +#define PIPEB_PP_STATUS 0x61300 > +#define PIPEB_PP_CONTROL 0x61304 > +#define PIPEB_PP_ON_DELAYS 0x61308 > +#define PIPEB_PP_OFF_DELAYS 0x6130c > +#define PIPEB_PP_DIVISOR 0x61310 > + > #define PCH_PP_STATUS 0xc7200 > #define PCH_PP_CONTROL 0xc7204 > #define PANEL_UNLOCK_REGS (0xabcd << 16) > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 6538c46..d59af24 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -342,7 +342,13 @@ static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) > struct drm_device *dev = intel_dp->base.base.dev; > struct drm_i915_private *dev_priv = dev->dev_private; > > - return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0; > + if (IS_VALLEYVIEW(dev)) { > + if (I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) > + return (I915_READ(PIPEB_PP_STATUS) & PP_ON) != 0; > + else > + return (I915_READ(PIPEA_PP_STATUS) & PP_ON) != 0; > + } else > + return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0; > } > > static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) ... I have a feeling that this patch should be much longer ;-) -Daniel -- Daniel Vetter Mail: daniel@ffwll.ch Mobile: +41 (0)79 365 57 48