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diff for duplicates of <20120622124311.GA21606@avionic-0098.mockup.avionic-design.de>

diff --git a/a/1.txt b/N1/1.txt
index 96c22cc..44e2d32 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -6,81 +6,81 @@ On Fri, Jun 22, 2012 at 05:46:52AM -0600, Bjorn Helgaas wrote:
 > >> <thierry.reding@avionic-design.de> wrote:
 > >> > On Tue, Jun 19, 2012 at 11:31:39AM -1000, Mitch Bradley wrote:
 > >>
-> >> >> Version A - 3 address cells:  In this version, the intermediate
-> >> >> address space has 3 cells:  port#, address type, offset.  Address
+> >> >> Version A - 3 address cells: ?In this version, the intermediate
+> >> >> address space has 3 cells: ?port#, address type, offset. ?Address
 > >> >> type is
-> >> >>   0 : root port
-> >> >>   1 : config space
-> >> >>   2 : extended config space
-> >> >>   3 : I/O
-> >> >>   4 : non-prefetchable memory
-> >> >>   5 : prefetchable memory.
+> >> >> ? 0 : root port
+> >> >> ? 1 : config space
+> >> >> ? 2 : extended config space
+> >> >> ? 3 : I/O
+> >> >> ? 4 : non-prefetchable memory
+> >> >> ? 5 : prefetchable memory.
 > >> >>
 > >> >> The third cell "offset" is necessary so that the size field has a
 > >> >> number space that can include it.
 > >> >>
-> >> >>       pcie-controller {
-> >> >>               compatible = "nvidia,tegra20-pcie";
-> >> >>               reg = <0x80003000 0x00000800   /* PADS registers */
-> >> >>                      0x80003800 0x00000200>; /* extended configuration space */
-> >> >>               interrupts = <0 98 0x04   /* controller interrupt */
-> >> >>                             0 99 0x04>; /* MSI interrupt */
-> >> >>               status = "disabled";
+> >> >> ? ? ? pcie-controller {
+> >> >> ? ? ? ? ? ? ? compatible = "nvidia,tegra20-pcie";
+> >> >> ? ? ? ? ? ? ? reg = <0x80003000 0x00000800 ? /* PADS registers */
+> >> >> ? ? ? ? ? ? ? ? ? ? ?0x80003800 0x00000200>; /* extended configuration space */
+> >> >> ? ? ? ? ? ? ? interrupts = <0 98 0x04 ? /* controller interrupt */
+> >> >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 99 0x04>; /* MSI interrupt */
+> >> >> ? ? ? ? ? ? ? status = "disabled";
 > >> >>
-> >> >>               ranges = <0 0 0  0x80000000 0x00001000   /* Root port 0 */
-> >> >>                         0 1 0  0x80004000 0x00080000   /* Port 0 config space */
-> >> >>                         0 2 0  0x80104000 0x00080000   /* Port 0 ext config space *
-> >> >>                         0 3 0  0x80400000 0x00008000   /* Port 0 downstream I/O */
-> >> >>                         0 4 0  0x90000000 0x08000000   /* Port 0 non-prefetchable memory */
-> >> >>                         0 5 0  0xa0000000 0x08000000   /* Port 0 prefetchable memory */
+> >> >> ? ? ? ? ? ? ? ranges = <0 0 0 ?0x80000000 0x00001000 ? /* Root port 0 */
+> >> >> ? ? ? ? ? ? ? ? ? ? ? ? 0 1 0 ?0x80004000 0x00080000 ? /* Port 0 config space */
+> >> >> ? ? ? ? ? ? ? ? ? ? ? ? 0 2 0 ?0x80104000 0x00080000 ? /* Port 0 ext config space *
+> >> >> ? ? ? ? ? ? ? ? ? ? ? ? 0 3 0 ?0x80400000 0x00008000 ? /* Port 0 downstream I/O */
+> >> >> ? ? ? ? ? ? ? ? ? ? ? ? 0 4 0 ?0x90000000 0x08000000 ? /* Port 0 non-prefetchable memory */
+> >> >> ? ? ? ? ? ? ? ? ? ? ? ? 0 5 0 ?0xa0000000 0x08000000 ? /* Port 0 prefetchable memory */
 > >> >>
-> >> >>                         1 0 0  0x80001000 0x00001000   /* Root port 1 */
-> >> >>                         1 1 0  0x80004000 0x00080000   /* Port 1 config space */
-> >> >>                         1 2 0  0x80184000 0x00080000   /* Port 1 ext config space */
-> >> >>                         1 3 0  0x80408000 0x00010000   /* Port 1 downstream I/O */
-> >> >>                         1 4 0  0x98000000 0x08000000   /* Port 1 non-prefetchable memory */
-> >> >>                         1 5 0  0xa0000000 0x08000000>; /* Port 1 prefetchable memory */
+> >> >> ? ? ? ? ? ? ? ? ? ? ? ? 1 0 0 ?0x80001000 0x00001000 ? /* Root port 1 */
+> >> >> ? ? ? ? ? ? ? ? ? ? ? ? 1 1 0 ?0x80004000 0x00080000 ? /* Port 1 config space */
+> >> >> ? ? ? ? ? ? ? ? ? ? ? ? 1 2 0 ?0x80184000 0x00080000 ? /* Port 1 ext config space */
+> >> >> ? ? ? ? ? ? ? ? ? ? ? ? 1 3 0 ?0x80408000 0x00010000 ? /* Port 1 downstream I/O */
+> >> >> ? ? ? ? ? ? ? ? ? ? ? ? 1 4 0 ?0x98000000 0x08000000 ? /* Port 1 non-prefetchable memory */
+> >> >> ? ? ? ? ? ? ? ? ? ? ? ? 1 5 0 ?0xa0000000 0x08000000>; /* Port 1 prefetchable memory */
 > >> >>
-> >> >>               #address-cells = <3>;
-> >> >>               #size-cells = <1>;
+> >> >> ? ? ? ? ? ? ? #address-cells = <3>;
+> >> >> ? ? ? ? ? ? ? #size-cells = <1>;
 > >> >>
-> >> >>               pci@0 {
-> >> >>                       reg = <0 0 0 0x1000>;
-> >> >>                       status = "disabled";
+> >> >> ? ? ? ? ? ? ? pci at 0 {
+> >> >> ? ? ? ? ? ? ? ? ? ? ? reg = <0 0 0 0x1000>;
+> >> >> ? ? ? ? ? ? ? ? ? ? ? status = "disabled";
 > >> >>
-> >> >>                       #address-cells = <3>;
-> >> >>                       #size-cells = <2>;
+> >> >> ? ? ? ? ? ? ? ? ? ? ? #address-cells = <3>;
+> >> >> ? ? ? ? ? ? ? ? ? ? ? #size-cells = <2>;
 > >> >>
-> >> >>                       ranges = <0x80000000 0 0  0 1 0  0 0x00080000   /* config */
-> >> >>                                 0x90000000 0 0  0 2 0  0 0x00080000   /* extended config */
-> >> >>                                 0x81000000 0 0  0 3 0  0 0x00008000   /* I/O */
-> >> >>                                 0x82000000 0 0  0 4 0  0 0x08000000   /* non-prefetchable memory */
-> >> >>                                 0xc2000000 0 0  0 5 0  0 0x08000000>; /* prefetchable memory */
+> >> >> ? ? ? ? ? ? ? ? ? ? ? ranges = <0x80000000 0 0 ?0 1 0 ?0 0x00080000 ? /* config */
+> >> >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x90000000 0 0 ?0 2 0 ?0 0x00080000 ? /* extended config */
+> >> >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x81000000 0 0 ?0 3 0 ?0 0x00008000 ? /* I/O */
+> >> >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x82000000 0 0 ?0 4 0 ?0 0x08000000 ? /* non-prefetchable memory */
+> >> >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0xc2000000 0 0 ?0 5 0 ?0 0x08000000>; /* prefetchable memory */
 > >> >>
-> >> >>                       nvidia,ctrl-offset = <0x110>;
-> >> >>                       nvidia,num-lanes = <2>;
-> >> >>               };
+> >> >> ? ? ? ? ? ? ? ? ? ? ? nvidia,ctrl-offset = <0x110>;
+> >> >> ? ? ? ? ? ? ? ? ? ? ? nvidia,num-lanes = <2>;
+> >> >> ? ? ? ? ? ? ? };
 > >> >>
 > >> >>
-> >> >>               pci@1 {
-> >> >>                       reg = <1 0 0 0x1000>;
-> >> >>                       status = "disabled";
+> >> >> ? ? ? ? ? ? ? pci at 1 {
+> >> >> ? ? ? ? ? ? ? ? ? ? ? reg = <1 0 0 0x1000>;
+> >> >> ? ? ? ? ? ? ? ? ? ? ? status = "disabled";
 > >> >>
-> >> >>                       #address-cells = <3>;
-> >> >>                       #size-cells = <2>;
+> >> >> ? ? ? ? ? ? ? ? ? ? ? #address-cells = <3>;
+> >> >> ? ? ? ? ? ? ? ? ? ? ? #size-cells = <2>;
 > >> >>
-> >> >>                       ranges = <0x80000000 0 0  1 1 0  0 0x00080000   /* config */
-> >> >>                                 0x90000000 0 0  1 2 0  0 0x00080000   /* extended config */
-> >> >>                                 0x81000000 0 0  1 3 0  0 0x00008000   /* I/O */
-> >> >>                                 0x82000000 0 0  1 4 0  0 0x08000000   /* non-prefetchable memory */
-> >> >>                                 0xc2000000 0 0  1 5 0  0 0x08000000>; /* prefetchable memory */
+> >> >> ? ? ? ? ? ? ? ? ? ? ? ranges = <0x80000000 0 0 ?1 1 0 ?0 0x00080000 ? /* config */
+> >> >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x90000000 0 0 ?1 2 0 ?0 0x00080000 ? /* extended config */
+> >> >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x81000000 0 0 ?1 3 0 ?0 0x00008000 ? /* I/O */
+> >> >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x82000000 0 0 ?1 4 0 ?0 0x08000000 ? /* non-prefetchable memory */
+> >> >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0xc2000000 0 0 ?1 5 0 ?0 0x08000000>; /* prefetchable memory */
 > >> >>
-> >> >>                       nvidia,ctrl-offset = <0x118>;
-> >> >>                       nvidia,num-lanes = <2>;
-> >> >>               };
+> >> >> ? ? ? ? ? ? ? ? ? ? ? nvidia,ctrl-offset = <0x118>;
+> >> >> ? ? ? ? ? ? ? ? ? ? ? nvidia,num-lanes = <2>;
+> >> >> ? ? ? ? ? ? ? };
 > >>
 > >> I'm not familiar with device tree, so pardon me if these are stupid
-> >> questions.  These seem to be describing PCI host bridges.
+> >> questions. ?These seem to be describing PCI host bridges.
 > >
 > > Yes, correct.
 > >
@@ -90,8 +90,8 @@ On Fri, Jun 22, 2012 at 05:46:52AM -0600, Bjorn Helgaas wrote:
 > > Yes.
 > >
 > >> Is there provision for any address offset applied by the bridge when
-> >> it forwards downstream?  (Maybe these bridges don't apply any offset?)
-> >>  "0xa0000000 0x08000000" appears for both ports 0 and 1 prefetchable
+> >> it forwards downstream? ?(Maybe these bridges don't apply any offset?)
+> >> ?"0xa0000000 0x08000000" appears for both ports 0 and 1 prefetchable
 > >> memory; I don't know if that's an error, an indication that each
 > >> bridge applies a different offset, or that both bridges forward the
 > >> same aperture (I hope not the latter, because Linux can't really deal
@@ -123,7 +123,7 @@ Each of the root ports has a PCI-compatible set of configuration
 registers, so I guess what is meant is that the apertures a programmed
 according to the PCI bridge specification.
 
-> >> Is the bus number aperture included somewhere?  How do we know what
+> >> Is the bus number aperture included somewhere? ?How do we know what
 > >> bus numbers are available for allocation under each bridge?
 > >
 > > Not yet. I don't think DT imposes a bus number allocation on PCI
@@ -158,7 +158,7 @@ Tegra PCIe controller even supports hot-plugging.
 > > them properly. I guess in the latter cases hard-coding the PCI tree in
 > > DT is not actually a drawback, though.
 > >
-> >> I see mention of config space.  Is some of that referring to the ECAM
+> >> I see mention of config space. ?Is some of that referring to the ECAM
 > >> as in 7.2.2 of the PCIe spec v3.0 (what we refer to as MMCONFIG on
 > >> x86)?
 > >
@@ -167,11 +167,11 @@ Tegra PCIe controller even supports hot-plugging.
 > > particular controller indeed implements something similar to ECAM. The
 > > address mapping is a little different, though:
 > >
-> >        A[(16 + n - 1):16]: bus number
-> >        A[15:11]: device number
-> >        A[10:8]: function number
-> >        A[7:2]: register number
-> >        A[1:0]: unused
+> > ? ? ? ?A[(16 + n - 1):16]: bus number
+> > ? ? ? ?A[15:11]: device number
+> > ? ? ? ?A[10:8]: function number
+> > ? ? ? ?A[7:2]: register number
+> > ? ? ? ?A[1:0]: unused
 > >
 > > That information comes directly from the driver and I have no access to
 > > the corresponding documentation. It seems like the extended
@@ -202,4 +202,11 @@ Since this is pretty well specified by PCIe, a generic implementation
 should be possible. We'll have to wait for some better documentation on
 Tegra to know whether this is actually ECAM or not.
 
-Thierry
\ No newline at end of file
+Thierry
+-------------- next part --------------
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diff --git a/a/2.bin b/a/2.bin
deleted file mode 100644
index a731e6d..0000000
--- a/a/2.bin
+++ /dev/null
@@ -1,17 +0,0 @@
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diff --git a/a/2.hdr b/a/2.hdr
deleted file mode 100644
index a09cc95..0000000
--- a/a/2.hdr
+++ /dev/null
@@ -1 +0,0 @@
-Content-Type: application/pgp-signature
diff --git a/a/content_digest b/N1/content_digest
index 94362aa..91ff6e4 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -29,32 +29,19 @@
   "ref\0CAErSpo6vHn3p96o7DSdL28cjapk2UnQ4ZVJ1oH6ksxbqD=Hh-g\@mail.gmail.com\0"
 ]
 [
-  "From\0Thierry Reding <thierry.reding\@avionic-design.de>\0"
+  "From\0thierry.reding\@avionic-design.de (Thierry Reding)\0"
 ]
 [
-  "Subject\0Re: [PATCH v2 07/10] ARM: tegra: pcie: Add device tree support\0"
+  "Subject\0[PATCH v2 07/10] ARM: tegra: pcie: Add device tree support\0"
 ]
 [
   "Date\0Fri, 22 Jun 2012 14:43:11 +0200\0"
 ]
 [
-  "To\0Bjorn Helgaas <bhelgaas\@google.com>\0"
+  "To\0linux-arm-kernel\@lists.infradead.org\0"
 ]
 [
-  "Cc\0Mitch Bradley <wmb\@firmworks.com>",
-  " Stephen Warren <swarren\@wwwdotorg.org>",
-  " Russell King <linux\@arm.linux.org.uk>",
-  " linux-pci\@vger.kernel.org",
-  " devicetree-discuss\@lists.ozlabs.org",
-  " Rob Herring <rob.herring\@calxeda.com>",
-  " Jesse Barnes <jbarnes\@virtuousgeek.org>",
-  " Colin Cross <ccross\@android.com>",
-  " linux-tegra\@vger.kernel.org",
-  " linux-arm-kernel\@lists.infradead.org",
-  " Arnd Bergmann <arnd\@arndb.de>\0"
-]
-[
-  "\0001:1\0"
+  "\0000:1\0"
 ]
 [
   "b\0"
@@ -68,81 +55,81 @@
   "> >> <thierry.reding\@avionic-design.de> wrote:\n",
   "> >> > On Tue, Jun 19, 2012 at 11:31:39AM -1000, Mitch Bradley wrote:\n",
   "> >>\n",
-  "> >> >> Version A - 3 address cells: \302\240In this version, the intermediate\n",
-  "> >> >> address space has 3 cells: \302\240port#, address type, offset. \302\240Address\n",
+  "> >> >> Version A - 3 address cells: ?In this version, the intermediate\n",
+  "> >> >> address space has 3 cells: ?port#, address type, offset. ?Address\n",
   "> >> >> type is\n",
-  "> >> >> \302\240 0 : root port\n",
-  "> >> >> \302\240 1 : config space\n",
-  "> >> >> \302\240 2 : extended config space\n",
-  "> >> >> \302\240 3 : I/O\n",
-  "> >> >> \302\240 4 : non-prefetchable memory\n",
-  "> >> >> \302\240 5 : prefetchable memory.\n",
+  "> >> >> ? 0 : root port\n",
+  "> >> >> ? 1 : config space\n",
+  "> >> >> ? 2 : extended config space\n",
+  "> >> >> ? 3 : I/O\n",
+  "> >> >> ? 4 : non-prefetchable memory\n",
+  "> >> >> ? 5 : prefetchable memory.\n",
   "> >> >>\n",
   "> >> >> The third cell \"offset\" is necessary so that the size field has a\n",
   "> >> >> number space that can include it.\n",
   "> >> >>\n",
-  "> >> >> \302\240 \302\240 \302\240 pcie-controller {\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 compatible = \"nvidia,tegra20-pcie\";\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 reg = <0x80003000 0x00000800 \302\240 /* PADS registers */\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\2400x80003800 0x00000200>; /* extended configuration space */\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 interrupts = <0 98 0x04 \302\240 /* controller interrupt */\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 0 99 0x04>; /* MSI interrupt */\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 status = \"disabled\";\n",
+  "> >> >> ? ? ? pcie-controller {\n",
+  "> >> >> ? ? ? ? ? ? ? compatible = \"nvidia,tegra20-pcie\";\n",
+  "> >> >> ? ? ? ? ? ? ? reg = <0x80003000 0x00000800 ? /* PADS registers */\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ?0x80003800 0x00000200>; /* extended configuration space */\n",
+  "> >> >> ? ? ? ? ? ? ? interrupts = <0 98 0x04 ? /* controller interrupt */\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 99 0x04>; /* MSI interrupt */\n",
+  "> >> >> ? ? ? ? ? ? ? status = \"disabled\";\n",
   "> >> >>\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 ranges = <0 0 0 \302\2400x80000000 0x00001000 \302\240 /* Root port 0 */\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 0 1 0 \302\2400x80004000 0x00080000 \302\240 /* Port 0 config space */\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 0 2 0 \302\2400x80104000 0x00080000 \302\240 /* Port 0 ext config space *\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 0 3 0 \302\2400x80400000 0x00008000 \302\240 /* Port 0 downstream I/O */\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 0 4 0 \302\2400x90000000 0x08000000 \302\240 /* Port 0 non-prefetchable memory */\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 0 5 0 \302\2400xa0000000 0x08000000 \302\240 /* Port 0 prefetchable memory */\n",
+  "> >> >> ? ? ? ? ? ? ? ranges = <0 0 0 ?0x80000000 0x00001000 ? /* Root port 0 */\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? ? 0 1 0 ?0x80004000 0x00080000 ? /* Port 0 config space */\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? ? 0 2 0 ?0x80104000 0x00080000 ? /* Port 0 ext config space *\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? ? 0 3 0 ?0x80400000 0x00008000 ? /* Port 0 downstream I/O */\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? ? 0 4 0 ?0x90000000 0x08000000 ? /* Port 0 non-prefetchable memory */\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? ? 0 5 0 ?0xa0000000 0x08000000 ? /* Port 0 prefetchable memory */\n",
   "> >> >>\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 1 0 0 \302\2400x80001000 0x00001000 \302\240 /* Root port 1 */\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 1 1 0 \302\2400x80004000 0x00080000 \302\240 /* Port 1 config space */\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 1 2 0 \302\2400x80184000 0x00080000 \302\240 /* Port 1 ext config space */\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 1 3 0 \302\2400x80408000 0x00010000 \302\240 /* Port 1 downstream I/O */\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 1 4 0 \302\2400x98000000 0x08000000 \302\240 /* Port 1 non-prefetchable memory */\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 1 5 0 \302\2400xa0000000 0x08000000>; /* Port 1 prefetchable memory */\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? ? 1 0 0 ?0x80001000 0x00001000 ? /* Root port 1 */\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? ? 1 1 0 ?0x80004000 0x00080000 ? /* Port 1 config space */\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? ? 1 2 0 ?0x80184000 0x00080000 ? /* Port 1 ext config space */\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? ? 1 3 0 ?0x80408000 0x00010000 ? /* Port 1 downstream I/O */\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? ? 1 4 0 ?0x98000000 0x08000000 ? /* Port 1 non-prefetchable memory */\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? ? 1 5 0 ?0xa0000000 0x08000000>; /* Port 1 prefetchable memory */\n",
   "> >> >>\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 #address-cells = <3>;\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 #size-cells = <1>;\n",
+  "> >> >> ? ? ? ? ? ? ? #address-cells = <3>;\n",
+  "> >> >> ? ? ? ? ? ? ? #size-cells = <1>;\n",
   "> >> >>\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 pci\@0 {\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 reg = <0 0 0 0x1000>;\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 status = \"disabled\";\n",
+  "> >> >> ? ? ? ? ? ? ? pci at 0 {\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? reg = <0 0 0 0x1000>;\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? status = \"disabled\";\n",
   "> >> >>\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 #address-cells = <3>;\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 #size-cells = <2>;\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? #address-cells = <3>;\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? #size-cells = <2>;\n",
   "> >> >>\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 ranges = <0x80000000 0 0 \302\2400 1 0 \302\2400 0x00080000 \302\240 /* config */\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 0x90000000 0 0 \302\2400 2 0 \302\2400 0x00080000 \302\240 /* extended config */\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 0x81000000 0 0 \302\2400 3 0 \302\2400 0x00008000 \302\240 /* I/O */\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 0x82000000 0 0 \302\2400 4 0 \302\2400 0x08000000 \302\240 /* non-prefetchable memory */\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 0xc2000000 0 0 \302\2400 5 0 \302\2400 0x08000000>; /* prefetchable memory */\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? ranges = <0x80000000 0 0 ?0 1 0 ?0 0x00080000 ? /* config */\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x90000000 0 0 ?0 2 0 ?0 0x00080000 ? /* extended config */\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x81000000 0 0 ?0 3 0 ?0 0x00008000 ? /* I/O */\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x82000000 0 0 ?0 4 0 ?0 0x08000000 ? /* non-prefetchable memory */\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0xc2000000 0 0 ?0 5 0 ?0 0x08000000>; /* prefetchable memory */\n",
   "> >> >>\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 nvidia,ctrl-offset = <0x110>;\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 nvidia,num-lanes = <2>;\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 };\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? nvidia,ctrl-offset = <0x110>;\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? nvidia,num-lanes = <2>;\n",
+  "> >> >> ? ? ? ? ? ? ? };\n",
   "> >> >>\n",
   "> >> >>\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 pci\@1 {\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 reg = <1 0 0 0x1000>;\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 status = \"disabled\";\n",
+  "> >> >> ? ? ? ? ? ? ? pci at 1 {\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? reg = <1 0 0 0x1000>;\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? status = \"disabled\";\n",
   "> >> >>\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 #address-cells = <3>;\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 #size-cells = <2>;\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? #address-cells = <3>;\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? #size-cells = <2>;\n",
   "> >> >>\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 ranges = <0x80000000 0 0 \302\2401 1 0 \302\2400 0x00080000 \302\240 /* config */\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 0x90000000 0 0 \302\2401 2 0 \302\2400 0x00080000 \302\240 /* extended config */\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 0x81000000 0 0 \302\2401 3 0 \302\2400 0x00008000 \302\240 /* I/O */\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 0x82000000 0 0 \302\2401 4 0 \302\2400 0x08000000 \302\240 /* non-prefetchable memory */\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 0xc2000000 0 0 \302\2401 5 0 \302\2400 0x08000000>; /* prefetchable memory */\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? ranges = <0x80000000 0 0 ?1 1 0 ?0 0x00080000 ? /* config */\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x90000000 0 0 ?1 2 0 ?0 0x00080000 ? /* extended config */\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x81000000 0 0 ?1 3 0 ?0 0x00008000 ? /* I/O */\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0x82000000 0 0 ?1 4 0 ?0 0x08000000 ? /* non-prefetchable memory */\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0xc2000000 0 0 ?1 5 0 ?0 0x08000000>; /* prefetchable memory */\n",
   "> >> >>\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 nvidia,ctrl-offset = <0x118>;\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 nvidia,num-lanes = <2>;\n",
-  "> >> >> \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 \302\240 };\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? nvidia,ctrl-offset = <0x118>;\n",
+  "> >> >> ? ? ? ? ? ? ? ? ? ? ? nvidia,num-lanes = <2>;\n",
+  "> >> >> ? ? ? ? ? ? ? };\n",
   "> >>\n",
   "> >> I'm not familiar with device tree, so pardon me if these are stupid\n",
-  "> >> questions. \302\240These seem to be describing PCI host bridges.\n",
+  "> >> questions. ?These seem to be describing PCI host bridges.\n",
   "> >\n",
   "> > Yes, correct.\n",
   "> >\n",
@@ -152,8 +139,8 @@
   "> > Yes.\n",
   "> >\n",
   "> >> Is there provision for any address offset applied by the bridge when\n",
-  "> >> it forwards downstream? \302\240(Maybe these bridges don't apply any offset?)\n",
-  "> >> \302\240\"0xa0000000 0x08000000\" appears for both ports 0 and 1 prefetchable\n",
+  "> >> it forwards downstream? ?(Maybe these bridges don't apply any offset?)\n",
+  "> >> ?\"0xa0000000 0x08000000\" appears for both ports 0 and 1 prefetchable\n",
   "> >> memory; I don't know if that's an error, an indication that each\n",
   "> >> bridge applies a different offset, or that both bridges forward the\n",
   "> >> same aperture (I hope not the latter, because Linux can't really deal\n",
@@ -185,7 +172,7 @@
   "registers, so I guess what is meant is that the apertures a programmed\n",
   "according to the PCI bridge specification.\n",
   "\n",
-  "> >> Is the bus number aperture included somewhere? \302\240How do we know what\n",
+  "> >> Is the bus number aperture included somewhere? ?How do we know what\n",
   "> >> bus numbers are available for allocation under each bridge?\n",
   "> >\n",
   "> > Not yet. I don't think DT imposes a bus number allocation on PCI\n",
@@ -220,7 +207,7 @@
   "> > them properly. I guess in the latter cases hard-coding the PCI tree in\n",
   "> > DT is not actually a drawback, though.\n",
   "> >\n",
-  "> >> I see mention of config space. \302\240Is some of that referring to the ECAM\n",
+  "> >> I see mention of config space. ?Is some of that referring to the ECAM\n",
   "> >> as in 7.2.2 of the PCIe spec v3.0 (what we refer to as MMCONFIG on\n",
   "> >> x86)?\n",
   "> >\n",
@@ -229,11 +216,11 @@
   "> > particular controller indeed implements something similar to ECAM. The\n",
   "> > address mapping is a little different, though:\n",
   "> >\n",
-  "> > \302\240 \302\240 \302\240 \302\240A[(16 + n - 1):16]: bus number\n",
-  "> > \302\240 \302\240 \302\240 \302\240A[15:11]: device number\n",
-  "> > \302\240 \302\240 \302\240 \302\240A[10:8]: function number\n",
-  "> > \302\240 \302\240 \302\240 \302\240A[7:2]: register number\n",
-  "> > \302\240 \302\240 \302\240 \302\240A[1:0]: unused\n",
+  "> > ? ? ? ?A[(16 + n - 1):16]: bus number\n",
+  "> > ? ? ? ?A[15:11]: device number\n",
+  "> > ? ? ? ?A[10:8]: function number\n",
+  "> > ? ? ? ?A[7:2]: register number\n",
+  "> > ? ? ? ?A[1:0]: unused\n",
   "> >\n",
   "> > That information comes directly from the driver and I have no access to\n",
   "> > the corresponding documentation. It seems like the extended\n",
@@ -264,32 +251,14 @@
   "should be possible. We'll have to wait for some better documentation on\n",
   "Tegra to know whether this is actually ECAM or not.\n",
   "\n",
-  "Thierry"
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+b9d6c758651e59baf621854c816cdfd95487d90c598d148baefca372d0dd5dc9
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