From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ben Widawsky Subject: Re: [PATCH 08/10] drm/i915: introduce haswell_init_clock_gating Date: Mon, 2 Jul 2012 11:39:32 -0700 Message-ID: <20120702113932.508d4c12@bwidawsk.net> References: <1341240671-5843-1-git-send-email-eugeni.dodonov@intel.com> <1341240671-5843-9-git-send-email-eugeni.dodonov@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from cloud01.chad-versace.us (184-106-247-128.static.cloud-ips.com [184.106.247.128]) by gabe.freedesktop.org (Postfix) with ESMTP id 88F789E7C8 for ; Mon, 2 Jul 2012 11:39:39 -0700 (PDT) In-Reply-To: <1341240671-5843-9-git-send-email-eugeni.dodonov@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Eugeni Dodonov Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, 2 Jul 2012 11:51:09 -0300 Eugeni Dodonov wrote: > This is based on Ivy Bridge clock gating for now, but is subject to > changes in the future. I am a fan of not including this until it's actually needed. I only took a peek, but I didn't see a need in the remaining patches. > > Signed-off-by: Eugeni Dodonov > --- > drivers/gpu/drm/i915/intel_pm.c | 54 ++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 53 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 5ea8319..f54196f 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3415,6 +3415,58 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) > I915_WRITE(GEN7_FF_THREAD_MODE, reg); > } > > +static void haswell_init_clock_gating(struct drm_device *dev) > +{ > + struct drm_i915_private *dev_priv = dev->dev_private; > + int pipe; > + uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; > + > + I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); > + > + I915_WRITE(WM3_LP_ILK, 0); > + I915_WRITE(WM2_LP_ILK, 0); > + I915_WRITE(WM1_LP_ILK, 0); > + > + /* According to the spec, bit 13 (RCZUNIT) must be set on IVB. > + * This implements the WaDisableRCZUnitClockGating workaround. > + */ > + I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); > + > + I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE); > + > + I915_WRITE(IVB_CHICKEN3, > + CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | > + CHICKEN3_DGMG_DONE_FIX_DISABLE); > + > + /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ > + I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, > + GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); > + > + /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ > + I915_WRITE(GEN7_L3CNTLREG1, > + GEN7_WA_FOR_GEN7_L3_CONTROL); > + I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, > + GEN7_WA_L3_CHICKEN_MODE); > + > + /* This is required by WaCatErrorRejectionIssue */ > + I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, > + I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | > + GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); > + > + for_each_pipe(pipe) { > + I915_WRITE(DSPCNTR(pipe), > + I915_READ(DSPCNTR(pipe)) | > + DISPPLANE_TRICKLE_FEED_DISABLE); > + intel_flush_display_plane(dev_priv, pipe); > + } > + > + gen7_setup_fixed_func_scheduler(dev_priv); > + > + /* WaDisable4x2SubspanOptimization */ > + I915_WRITE(CACHE_MODE_1, > + _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); > +} > + > static void ivybridge_init_clock_gating(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > @@ -3824,7 +3876,7 @@ void intel_init_pm(struct drm_device *dev) > "Disable CxSR\n"); > dev_priv->display.update_wm = NULL; > } > - dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; > + dev_priv->display.init_clock_gating = haswell_init_clock_gating; > dev_priv->display.sanitize_pm = gen6_sanitize_pm; > } else > dev_priv->display.update_wm = NULL; -- Ben Widawsky, Intel Open Source Technology Center