From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:37475) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TQEgH-0007mM-9J for qemu-devel@nongnu.org; Mon, 22 Oct 2012 05:52:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TQEgG-00060S-0f for qemu-devel@nongnu.org; Mon, 22 Oct 2012 05:52:21 -0400 Received: from mx1.redhat.com ([209.132.183.28]:8481) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TQEgF-00060O-OO for qemu-devel@nongnu.org; Mon, 22 Oct 2012 05:52:19 -0400 Date: Mon, 22 Oct 2012 12:54:20 +0200 From: "Michael S. Tsirkin" Message-ID: <20121022105420.GG28828@redhat.com> References: <24b7d8736b55f284b13990be93dcdfd06d471cfc.1350677361.git.jbaron@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <24b7d8736b55f284b13990be93dcdfd06d471cfc.1350677361.git.jbaron@redhat.com> Subject: Re: [Qemu-devel] [PATCH v3 10/26] pcie: pass pcie window size to pcie_host_mmcfg_update() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Jason Baron Cc: agraf@suse.de, aliguori@us.ibm.com, juzhang@redhat.com, jan.kiszka@siemens.com, qemu-devel@nongnu.org, armbru@redhat.com, blauwirbel@gmail.com, yamahata@valinux.co.jp, alex.williamson@redhat.com, kevin@koconnor.net, avi@redhat.com, mkletzan@redhat.com, pbonzini@redhat.com, lcapitulino@redhat.com, afaerber@suse.de, kraxel@redhat.com On Fri, Oct 19, 2012 at 04:43:32PM -0400, Jason Baron wrote: > From: Jason Baron > > This allows q35 to pass/set the size of the pcie window in its update routine. > > Reviewed-by: Paolo Bonzini > Signed-off-by: Jason Baron Applied, thanks. > --- > hw/pcie_host.c | 21 ++++++++++++--------- > hw/pcie_host.h | 8 +++++--- > 2 files changed, 17 insertions(+), 12 deletions(-) > > diff --git a/hw/pcie_host.c b/hw/pcie_host.c > index 28bbe72..e2fd276 100644 > --- a/hw/pcie_host.c > +++ b/hw/pcie_host.c > @@ -107,14 +107,9 @@ static const MemoryRegionOps pcie_mmcfg_ops = { > /* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */ > #define PCIE_BASE_ADDR_UNMAPPED ((target_phys_addr_t)-1ULL) > > -int pcie_host_init(PCIExpressHost *e, uint32_t size) > +int pcie_host_init(PCIExpressHost *e) > { > - assert(!(size & (size - 1))); /* power of 2 */ > - assert(size >= PCIE_MMCFG_SIZE_MIN); > - assert(size <= PCIE_MMCFG_SIZE_MAX); > e->base_addr = PCIE_BASE_ADDR_UNMAPPED; > - e->size = size; > - memory_region_init_io(&e->mmio, &pcie_mmcfg_ops, e, "pcie-mmcfg", e->size); > > return 0; > } > @@ -123,22 +118,30 @@ void pcie_host_mmcfg_unmap(PCIExpressHost *e) > { > if (e->base_addr != PCIE_BASE_ADDR_UNMAPPED) { > memory_region_del_subregion(get_system_memory(), &e->mmio); > + memory_region_destroy(&e->mmio); > e->base_addr = PCIE_BASE_ADDR_UNMAPPED; > } > } > > -void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr) > +void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr, > + uint32_t size) > { > + assert(!(size & (size - 1))); /* power of 2 */ > + assert(size >= PCIE_MMCFG_SIZE_MIN); > + assert(size <= PCIE_MMCFG_SIZE_MAX); > + e->size = size; > + memory_region_init_io(&e->mmio, &pcie_mmcfg_ops, e, "pcie-mmcfg", e->size); > e->base_addr = addr; > memory_region_add_subregion(get_system_memory(), e->base_addr, &e->mmio); > } > > void pcie_host_mmcfg_update(PCIExpressHost *e, > int enable, > - target_phys_addr_t addr) > + target_phys_addr_t addr, > + uint32_t size) > { > pcie_host_mmcfg_unmap(e); > if (enable) { > - pcie_host_mmcfg_map(e, addr); > + pcie_host_mmcfg_map(e, addr, size); > } > } > diff --git a/hw/pcie_host.h b/hw/pcie_host.h > index 0074508..2faa54e 100644 > --- a/hw/pcie_host.h > +++ b/hw/pcie_host.h > @@ -39,11 +39,13 @@ struct PCIExpressHost { > MemoryRegion mmio; > }; > > -int pcie_host_init(PCIExpressHost *e, uint32_t size); > +int pcie_host_init(PCIExpressHost *e); > void pcie_host_mmcfg_unmap(PCIExpressHost *e); > -void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr); > +void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr, > + uint32_t size); > void pcie_host_mmcfg_update(PCIExpressHost *e, > int enable, > - target_phys_addr_t addr); > + target_phys_addr_t addr, > + uint32_t size); > > #endif /* PCIE_HOST_H */ > -- > 1.7.1