From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.free-electrons.com ([94.23.35.102]:57609 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758411Ab3BGRhs (ORCPT ); Thu, 7 Feb 2013 12:37:48 -0500 Date: Thu, 7 Feb 2013 18:37:43 +0100 From: Thomas Petazzoni To: Andrew Murray Cc: Bjorn Helgaas , "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Jason Cooper , Andrew Lunn , Gregory Clement , Arnd Bergmann , Maen Suleiman , Lior Amsalem , Thierry Reding , Eran Ben-Avi , Nadav Haklai , Shadi Ammouri , Tawfik Bayouk , Stephen Warren , Jason Gunthorpe , Russell King - ARM Linux Subject: Re: [PATCH v2 19/27] pci: PCIe driver for Marvell Armada 370/XP systems Message-ID: <20130207183743.5c97d8b8@skate> In-Reply-To: <20130207172934.GA2811@arm.com> References: <1359399397-29729-1-git-send-email-thomas.petazzoni@free-electrons.com> <1359399397-29729-20-git-send-email-thomas.petazzoni@free-electrons.com> <20130129132204.GA23886@arm.com> <20130207153750.0fef1192@skate> <20130207155117.GA19666@arm.com> <20130207171904.70270598@skate> <20130207174040.3a345770@skate> <20130207165347.GA31995@arm.com> <20130207181418.3753b007@skate> <20130207172934.GA2811@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-pci-owner@vger.kernel.org List-ID: Dear Andrew Murray, On Thu, 7 Feb 2013 17:29:34 +0000, Andrew Murray wrote: > > So if I ignore the bus number, how could the PCI code find what is the > > matching interrupt? > > Apologies if I've missed information about your hardware in the other > discussion (I've tried to keep up) - does your hardware raise a single host > interrupt for each pin regardless to which bridge they come in on - or do you > separate A,B,C,D host interrupts for each bridge? There are separate A,B,C,D interrupts for each PCIe interface, and each PCIe interface is represented by an emulated PCI-to-PCI bridge. See my interrupt-map: interrupt-map = <0x0800 0 0 1 &mpic 58 0x1000 0 0 1 &mpic 59 0x1800 0 0 1 &mpic 60 0x2000 0 0 1 &mpic 61 0x2800 0 0 1 &mpic 62 0x3000 0 0 1 &mpic 63 0x3800 0 0 1 &mpic 64 0x4000 0 0 1 &mpic 65 0x4800 0 0 1 &mpic 99 0x5000 0 0 1 &mpic 103>; Here I have 10 PCIe interfaces, and therefore 10 interrupts. There is only one interrupt per PCIe interface, and for now, I don't distinguish A,B,C,D (I will do it later, it requires reading a register to know if the interrupt came from A, B, C or D, but that's a different problem). > If you have only 4 interrupt sources for legacy interrupts then you shouldn't > need to care which bus/device/function they were generated on (of_pci_map_irq > takes care of this for you). No, I have interrupts per PCIe interface, so I really need to take care of the relation between the PCIe device and the PCIe interface it is connected to. Thomas -- Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com From mboxrd@z Thu Jan 1 00:00:00 1970 From: thomas.petazzoni@free-electrons.com (Thomas Petazzoni) Date: Thu, 7 Feb 2013 18:37:43 +0100 Subject: [PATCH v2 19/27] pci: PCIe driver for Marvell Armada 370/XP systems In-Reply-To: <20130207172934.GA2811@arm.com> References: <1359399397-29729-1-git-send-email-thomas.petazzoni@free-electrons.com> <1359399397-29729-20-git-send-email-thomas.petazzoni@free-electrons.com> <20130129132204.GA23886@arm.com> <20130207153750.0fef1192@skate> <20130207155117.GA19666@arm.com> <20130207171904.70270598@skate> <20130207174040.3a345770@skate> <20130207165347.GA31995@arm.com> <20130207181418.3753b007@skate> <20130207172934.GA2811@arm.com> Message-ID: <20130207183743.5c97d8b8@skate> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Dear Andrew Murray, On Thu, 7 Feb 2013 17:29:34 +0000, Andrew Murray wrote: > > So if I ignore the bus number, how could the PCI code find what is the > > matching interrupt? > > Apologies if I've missed information about your hardware in the other > discussion (I've tried to keep up) - does your hardware raise a single host > interrupt for each pin regardless to which bridge they come in on - or do you > separate A,B,C,D host interrupts for each bridge? There are separate A,B,C,D interrupts for each PCIe interface, and each PCIe interface is represented by an emulated PCI-to-PCI bridge. See my interrupt-map: interrupt-map = <0x0800 0 0 1 &mpic 58 0x1000 0 0 1 &mpic 59 0x1800 0 0 1 &mpic 60 0x2000 0 0 1 &mpic 61 0x2800 0 0 1 &mpic 62 0x3000 0 0 1 &mpic 63 0x3800 0 0 1 &mpic 64 0x4000 0 0 1 &mpic 65 0x4800 0 0 1 &mpic 99 0x5000 0 0 1 &mpic 103>; Here I have 10 PCIe interfaces, and therefore 10 interrupts. There is only one interrupt per PCIe interface, and for now, I don't distinguish A,B,C,D (I will do it later, it requires reading a register to know if the interrupt came from A, B, C or D, but that's a different problem). > If you have only 4 interrupt sources for legacy interrupts then you shouldn't > need to care which bus/device/function they were generated on (of_pci_map_irq > takes care of this for you). No, I have interrupts per PCIe interface, so I really need to take care of the relation between the PCIe device and the PCIe interface it is connected to. Thomas -- Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com