* [PATCH 2/2] x86,AMD: Enable WC+ memory type on family 10 processors @ 2013-01-29 21:32 Boris Ostrovsky 2013-01-31 22:45 ` [tip:x86/cpu] x86, AMD: " tip-bot for Boris Ostrovsky 0 siblings, 1 reply; 7+ messages in thread From: Boris Ostrovsky @ 2013-01-29 21:32 UTC (permalink / raw) To: tglx, mingo, hpa; +Cc: Jacob.Shin, bp, linux-kernel, Boris Ostrovsky From: Boris Ostrovsky <boris.ostrovsky@amd.com> In some cases BIOS may not enable WC+ memory type on family 10 processors, instead converting what would be WC+ memory to CD type. On guests using nested pages this could result in performance degradation. This patch enables WC+. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@amd.com> --- arch/x86/include/uapi/asm/msr-index.h | 1 + arch/x86/kernel/cpu/amd.c | 21 ++++++++++++++++----- 2 files changed, 17 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h index 433a59f..158cde9 100644 --- a/arch/x86/include/uapi/asm/msr-index.h +++ b/arch/x86/include/uapi/asm/msr-index.h @@ -173,6 +173,7 @@ #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 #define MSR_AMD64_OSVW_STATUS 0xc0010141 #define MSR_AMD64_DC_CFG 0xc0011022 +#define MSR_AMD64_BU_CFG2 0xc001102a #define MSR_AMD64_IBSFETCHCTL 0xc0011030 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index dd4a5b6..721ef32 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -698,13 +698,11 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) if (c->x86 > 0x11) set_cpu_cap(c, X86_FEATURE_ARAT); - /* - * Disable GART TLB Walk Errors on Fam10h. We do this here - * because this is always needed when GART is enabled, even in a - * kernel which has no MCE support built in. - */ if (c->x86 == 0x10) { /* + * Disable GART TLB Walk Errors on Fam10h. We do this here + * because this is always needed when GART is enabled, even in a + * kernel which has no MCE support built in. * BIOS should disable GartTlbWlk Errors themself. If * it doesn't do it here as suggested by the BKDG. * @@ -718,6 +716,19 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) mask |= (1 << 10); wrmsrl_safe(MSR_AMD64_MCx_MASK(4), mask); } + + /* + * On family 10h BIOS may not have properly enabled WC+ support, + * causing it to be converted to CD memtype. This may result in + * performance degradation for certain nested-paging guests. + * Prevent this conversion by clearing bit 24 in + * MSR_AMD64_BU_CFG2. + */ + if (c->x86 == 0x10) { + rdmsrl(MSR_AMD64_BU_CFG2, value); + value &= ~(1ULL << 24); + wrmsrl(MSR_AMD64_BU_CFG2, value); + } } rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); -- 1.7.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [tip:x86/cpu] x86, AMD: Enable WC+ memory type on family 10 processors 2013-01-29 21:32 [PATCH 2/2] x86,AMD: Enable WC+ memory type on family 10 processors Boris Ostrovsky @ 2013-01-31 22:45 ` tip-bot for Boris Ostrovsky 2013-02-13 0:16 ` Borislav Petkov 0 siblings, 1 reply; 7+ messages in thread From: tip-bot for Boris Ostrovsky @ 2013-01-31 22:45 UTC (permalink / raw) To: linux-tip-commits; +Cc: linux-kernel, hpa, mingo, boris.ostrovsky, tglx, hpa Commit-ID: f0322bd341fd63261527bf84afd3272bcc2e8dd3 Gitweb: http://git.kernel.org/tip/f0322bd341fd63261527bf84afd3272bcc2e8dd3 Author: Boris Ostrovsky <boris.ostrovsky@amd.com> AuthorDate: Tue, 29 Jan 2013 16:32:49 -0500 Committer: H. Peter Anvin <hpa@linux.intel.com> CommitDate: Thu, 31 Jan 2013 13:35:38 -0800 x86, AMD: Enable WC+ memory type on family 10 processors In some cases BIOS may not enable WC+ memory type on family 10 processors, instead converting what would be WC+ memory to CD type. On guests using nested pages this could result in performance degradation. This patch enables WC+. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@amd.com> Link: http://lkml.kernel.org/r/1359495169-23278-1-git-send-email-ostr@amd64.org Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> --- arch/x86/include/uapi/asm/msr-index.h | 1 + arch/x86/kernel/cpu/amd.c | 21 ++++++++++++++++----- 2 files changed, 17 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h index 433a59f..158cde9 100644 --- a/arch/x86/include/uapi/asm/msr-index.h +++ b/arch/x86/include/uapi/asm/msr-index.h @@ -173,6 +173,7 @@ #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 #define MSR_AMD64_OSVW_STATUS 0xc0010141 #define MSR_AMD64_DC_CFG 0xc0011022 +#define MSR_AMD64_BU_CFG2 0xc001102a #define MSR_AMD64_IBSFETCHCTL 0xc0011030 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index dd4a5b6..721ef32 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -698,13 +698,11 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) if (c->x86 > 0x11) set_cpu_cap(c, X86_FEATURE_ARAT); - /* - * Disable GART TLB Walk Errors on Fam10h. We do this here - * because this is always needed when GART is enabled, even in a - * kernel which has no MCE support built in. - */ if (c->x86 == 0x10) { /* + * Disable GART TLB Walk Errors on Fam10h. We do this here + * because this is always needed when GART is enabled, even in a + * kernel which has no MCE support built in. * BIOS should disable GartTlbWlk Errors themself. If * it doesn't do it here as suggested by the BKDG. * @@ -718,6 +716,19 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) mask |= (1 << 10); wrmsrl_safe(MSR_AMD64_MCx_MASK(4), mask); } + + /* + * On family 10h BIOS may not have properly enabled WC+ support, + * causing it to be converted to CD memtype. This may result in + * performance degradation for certain nested-paging guests. + * Prevent this conversion by clearing bit 24 in + * MSR_AMD64_BU_CFG2. + */ + if (c->x86 == 0x10) { + rdmsrl(MSR_AMD64_BU_CFG2, value); + value &= ~(1ULL << 24); + wrmsrl(MSR_AMD64_BU_CFG2, value); + } } rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [tip:x86/cpu] x86, AMD: Enable WC+ memory type on family 10 processors 2013-01-31 22:45 ` [tip:x86/cpu] x86, AMD: " tip-bot for Boris Ostrovsky @ 2013-02-13 0:16 ` Borislav Petkov 2013-02-13 0:21 ` H. Peter Anvin 0 siblings, 1 reply; 7+ messages in thread From: Borislav Petkov @ 2013-02-13 0:16 UTC (permalink / raw) To: mingo, hpa, linux-kernel, boris.ostrovsky, tglx, hpa; +Cc: linux-tip-commits Two issues I got with this one, see below. On Thu, Jan 31, 2013 at 02:45:06PM -0800, tip-bot for Boris Ostrovsky wrote: > Commit-ID: f0322bd341fd63261527bf84afd3272bcc2e8dd3 > Gitweb: http://git.kernel.org/tip/f0322bd341fd63261527bf84afd3272bcc2e8dd3 > Author: Boris Ostrovsky <boris.ostrovsky@amd.com> > AuthorDate: Tue, 29 Jan 2013 16:32:49 -0500 > Committer: H. Peter Anvin <hpa@linux.intel.com> > CommitDate: Thu, 31 Jan 2013 13:35:38 -0800 > > x86, AMD: Enable WC+ memory type on family 10 processors > > In some cases BIOS may not enable WC+ memory type on family 10 > processors, instead converting what would be WC+ memory to CD type. > On guests using nested pages this could result in performance > degradation. This patch enables WC+. > > Signed-off-by: Boris Ostrovsky <boris.ostrovsky@amd.com> > Link: http://lkml.kernel.org/r/1359495169-23278-1-git-send-email-ostr@amd64.org > Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> > --- > arch/x86/include/uapi/asm/msr-index.h | 1 + > arch/x86/kernel/cpu/amd.c | 21 ++++++++++++++++----- > 2 files changed, 17 insertions(+), 5 deletions(-) > > diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h > index 433a59f..158cde9 100644 > --- a/arch/x86/include/uapi/asm/msr-index.h > +++ b/arch/x86/include/uapi/asm/msr-index.h > @@ -173,6 +173,7 @@ > #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 > #define MSR_AMD64_OSVW_STATUS 0xc0010141 > #define MSR_AMD64_DC_CFG 0xc0011022 > +#define MSR_AMD64_BU_CFG2 0xc001102a > #define MSR_AMD64_IBSFETCHCTL 0xc0011030 > #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 > #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 > diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c > index dd4a5b6..721ef32 100644 > --- a/arch/x86/kernel/cpu/amd.c > +++ b/arch/x86/kernel/cpu/amd.c > @@ -698,13 +698,11 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) > if (c->x86 > 0x11) > set_cpu_cap(c, X86_FEATURE_ARAT); > > - /* > - * Disable GART TLB Walk Errors on Fam10h. We do this here > - * because this is always needed when GART is enabled, even in a > - * kernel which has no MCE support built in. > - */ > if (c->x86 == 0x10) { > /* > + * Disable GART TLB Walk Errors on Fam10h. We do this here > + * because this is always needed when GART is enabled, even in a > + * kernel which has no MCE support built in. > * BIOS should disable GartTlbWlk Errors themself. If > * it doesn't do it here as suggested by the BKDG. > * > @@ -718,6 +716,19 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) > mask |= (1 << 10); > wrmsrl_safe(MSR_AMD64_MCx_MASK(4), mask); > } > + > + /* > + * On family 10h BIOS may not have properly enabled WC+ support, > + * causing it to be converted to CD memtype. This may result in > + * performance degradation for certain nested-paging guests. > + * Prevent this conversion by clearing bit 24 in > + * MSR_AMD64_BU_CFG2. > + */ > + if (c->x86 == 0x10) { This family check is redundant, we're already in a 0x10 if-branch above. Boris had sent a second version which doesn't have that check: http://marc.info/?l=linux-kernel&m=135949774114910 but I don't know how this other version has gotten in. @hpa: maybe replace - patch is still at the top of tip:x86/cpu? > + rdmsrl(MSR_AMD64_BU_CFG2, value); > + value &= ~(1ULL << 24); > + wrmsrl(MSR_AMD64_BU_CFG2, value); > + } > } > > rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); However, the more serious issue is that that same kernel #GPs when booted in kvm. It seems it cannot stomach that specific MSR, see the second "<-- trapping instruction" below and that BU_CFG2 MSR landing in %ecx in the line before that. Oh, and this happens only with the kvm executable (/usr/bin/kvm) in debian testing. If I use qemu from git, it passes over init_amd just fine. Hmmm.. [ 0.018000] general protection fault: 0000 [#1] PREEMPT SMP [ 0.018000] Modules linked in: [ 0.018000] CPU 0 [ 0.018000] Pid: 0, comm: swapper/0 Not tainted 3.8.0-rc6+ #3 Bochs Bochs [ 0.018000] RIP: 0010:[<ffffffff81581a48>] [<ffffffff81581a48>] init_amd+0x4d6/0x50d [ 0.018000] RSP: 0000:ffffffff81813ed8 EFLAGS: 00010246 [ 0.018000] RAX: 0000000000000000 RBX: 0000000000726f73 RCX: 00000000c001102a [ 0.018000] RDX: ffffffff8268b021 RSI: 00000000fffffffb RDI: 0000000000000005 [ 0.018000] RBP: ffffffff81813f28 R08: 0000000000000000 R09: 0000000000000000 [ 0.018000] R10: 0000000000000001 R11: 0000000000000000 R12: ffffffff8189e140 [ 0.018000] R13: ffffffff81af82e0 R14: ffff88007ffd0300 R15: 0000000000000000 [ 0.018000] FS: 0000000000000000(0000) GS:ffff88007fc00000(0000) knlGS:0000000000000000 [ 0.018000] CS: 0010 DS: 0000 ES: 0000 CR0: 000000008005003b [ 0.018000] CR2: ffff88000268c000 CR3: 000000000181e000 CR4: 00000000000006b0 [ 0.018000] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 0.018000] DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400 [ 0.018000] Process swapper/0 (pid: 0, threadinfo ffffffff81812000, task ffffffff81823440) [ 0.018000] Stack: [ 0.018000] ffff88007d02d300 ffff88007d032000 ffffffff817689ca 0000000000000001 [ 0.018000] 0000001000000001 0000000000726f73 ffffffff8189e140 ffffffff81af82e0 [ 0.018000] ffff88007ffd0300 0000000000000000 ffffffff81813f48 ffffffff81580773 [ 0.018000] Call Trace: [ 0.018000] [<ffffffff81580773>] identify_cpu+0x245/0x3c3 [ 0.018000] [<ffffffff81a816a9>] identify_boot_cpu+0x10/0x3c [ 0.018000] [<ffffffff81a8194c>] check_bugs+0x9/0x2d [ 0.018000] [<ffffffff81a7cd10>] start_kernel+0x2c5/0x2e1 [ 0.018000] [<ffffffff81a7c84a>] ? repair_env_string+0x5e/0x5e [ 0.018000] [<ffffffff81a7c57c>] x86_64_start_reservations+0x2a/0x2c [ 0.018000] [<ffffffff81a7c646>] x86_64_start_kernel+0xc8/0xcc [ 0.018000] Code: 0f 32 31 f6 85 f6 75 17 48 c1 e2 20 0d 00 04 00 00 48 09 d0 48 89 c2 48 c1 ea 20 0f 30 31 c0 41 80 3c 24 10 75 1c b9 2a 10 01 c0 <0f> 32 48 c1 e2 20 25 ff ff ff fe 48 09 d0 48 89 c2 48 c1 ea 20 [ 0.018000] RIP [<ffffffff81581a48>] init_amd+0x4d6/0x50d [ 0.018000] RSP <ffffffff81813ed8> [ 0.019000] ---[ end trace 12a5c70bed5abe42 ]--- [ 0.020000] Kernel panic - not syncing: Attempted to kill the idle task! [ 0.018000] Code: 0f 32 31 f6 85 f6 75 17 48 c1 e2 20 0d 00 04 00 00 48 09 d0 48 89 c2 48 c1 ea 20 0f 30 31 c0 41 80 3c 24 10 75 1c b9 2a 10 01 c0 <0f> 32 48 c1 e2 20 25 ff ff ff fe 48 09 d0 48 89 c2 48 c1 ea 20 All code ======== 0:* 0f 32 rdmsr <-- trapping instruction 2: 31 f6 xor %esi,%esi 4: 85 f6 test %esi,%esi 6: 75 17 jne 0x1f 8: 48 c1 e2 20 shl $0x20,%rdx c: 0d 00 04 00 00 or $0x400,%eax 11: 48 09 d0 or %rdx,%rax 14: 48 89 c2 mov %rax,%rdx 17: 48 c1 ea 20 shr $0x20,%rdx 1b: 0f 30 wrmsr 1d: 31 c0 xor %eax,%eax 1f: 41 80 3c 24 10 cmpb $0x10,(%r12) 24: 75 1c jne 0x42 26: b9 2a 10 01 c0 mov $0xc001102a,%ecx 2b:* 0f 32 rdmsr <-- trapping instruction 2d: 48 c1 e2 20 shl $0x20,%rdx 31: 25 ff ff ff fe and $0xfeffffff,%eax 36: 48 09 d0 or %rdx,%rax 39: 48 89 c2 mov %rax,%rdx 3c: 48 c1 ea 20 shr $0x20,%rdx -- Regards/Gruss, Boris. Sent from a fat crate under my desk. Formatting is fine. -- ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [tip:x86/cpu] x86, AMD: Enable WC+ memory type on family 10 processors 2013-02-13 0:16 ` Borislav Petkov @ 2013-02-13 0:21 ` H. Peter Anvin 2013-02-13 0:31 ` Borislav Petkov 2013-02-13 8:06 ` Pekka Enberg 0 siblings, 2 replies; 7+ messages in thread From: H. Peter Anvin @ 2013-02-13 0:21 UTC (permalink / raw) To: Borislav Petkov, mingo, linux-kernel, boris.ostrovsky, tglx, hpa, linux-tip-commits Cc: Pekka Enberg On 02/12/2013 04:16 PM, Borislav Petkov wrote: > > This family check is redundant, we're already in a 0x10 if-branch > above. Boris had sent a second version which doesn't have that check: > http://marc.info/?l=linux-kernel&m=135949774114910 but I don't know how this > other version has gotten in. > > @hpa: maybe replace - patch is still at the top of tip:x86/cpu? > I'll check with Ingo if that is doable. >> + rdmsrl(MSR_AMD64_BU_CFG2, value); >> + value &= ~(1ULL << 24); >> + wrmsrl(MSR_AMD64_BU_CFG2, value); >> + } >> } >> >> rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); > > However, the more serious issue is that that same kernel #GPs when > booted in kvm. It seems it cannot stomach that specific MSR, see the > second "<-- trapping instruction" below and that BU_CFG2 MSR landing in > %ecx in the line before that. > > Oh, and this happens only with the kvm executable (/usr/bin/kvm) in > debian testing. If I use qemu from git, it passes over init_amd just > fine. > > Hmmm.. > It #GPs on an MSR, which tends to be a bug in the VMM; RDMSR/WRMSR generally kick out to the VMM. There isn't a huge lot of work we can do about that... I think Qemu defaults to ignoring unknown-to-it MSRs whereas maybe kvmtool croaks? Pekka? -hpa -- H. Peter Anvin, Intel Open Source Technology Center I work for Intel. I don't speak on their behalf. ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [tip:x86/cpu] x86, AMD: Enable WC+ memory type on family 10 processors 2013-02-13 0:21 ` H. Peter Anvin @ 2013-02-13 0:31 ` Borislav Petkov 2013-02-13 8:06 ` Pekka Enberg 1 sibling, 0 replies; 7+ messages in thread From: Borislav Petkov @ 2013-02-13 0:31 UTC (permalink / raw) To: H. Peter Anvin Cc: mingo, linux-kernel, boris.ostrovsky, tglx, hpa, linux-tip-commits, Pekka Enberg, kvm On Tue, Feb 12, 2013 at 04:21:13PM -0800, H. Peter Anvin wrote: > On 02/12/2013 04:16 PM, Borislav Petkov wrote: > > > >This family check is redundant, we're already in a 0x10 if-branch > >above. Boris had sent a second version which doesn't have that check: > >http://marc.info/?l=linux-kernel&m=135949774114910 but I don't know how this > >other version has gotten in. > > > >@hpa: maybe replace - patch is still at the top of tip:x86/cpu? > > > > I'll check with Ingo if that is doable. > > >>+ rdmsrl(MSR_AMD64_BU_CFG2, value); > >>+ value &= ~(1ULL << 24); > >>+ wrmsrl(MSR_AMD64_BU_CFG2, value); > >>+ } > >> } > >> > >> rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); > > > >However, the more serious issue is that that same kernel #GPs when > >booted in kvm. It seems it cannot stomach that specific MSR, see the > >second "<-- trapping instruction" below and that BU_CFG2 MSR landing in > >%ecx in the line before that. > > > >Oh, and this happens only with the kvm executable (/usr/bin/kvm) in > >debian testing. If I use qemu from git, it passes over init_amd just > >fine. > > > >Hmmm.. > > > > It #GPs on an MSR, which tends to be a bug in the VMM; RDMSR/WRMSR > generally kick out to the VMM. There isn't a huge lot of work we > can do about that... Yeah, kvm.ko which runs on the host says that it ignores this MSR: [160716.170333] kvm [29093]: vcpu0 unhandled rdmsr: 0xc001102a > I think Qemu defaults to ignoring unknown-to-it MSRs whereas maybe > kvmtool croaks? Pekka? Actually that's the qemu kvm thing you get from http://www.linux-kvm.org not the kvmtool. Let me add the kvm ML to CC. Guys, when I start the guest in kvm, it #GPs early when it tries to RDMSR 0xc001102a. Here's the oops message: http://marc.info/?l=linux-kernel&m=136071460803452 qemu-kvm is qemu-kvm (1.1.2+dfsg-5) from debian testing. Command line is: kvm -snapshot -gdb tcp::1234 -cpu phenom -hda /home/boris/kvm/debian/sid-x86_64.img -name "Debian x86_64:1235" -boot menu=off,order=c -m 2048 -localtime -net nic -net user,hostfwd=tcp::1235-:22 -usbdevice tablet -kernel /w/kernel/linux-2.6/arch/x86/boot/bzImage -append "vga=0 root=/dev/sda1 debug ignore_loglevel console=ttyS0,115200 console=tty0" -serial file:/home/boris/kvm/test-x86_64.log Any ideas? -- Regards/Gruss, Boris. Sent from a fat crate under my desk. Formatting is fine. -- ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [tip:x86/cpu] x86, AMD: Enable WC+ memory type on family 10 processors 2013-02-13 0:21 ` H. Peter Anvin 2013-02-13 0:31 ` Borislav Petkov @ 2013-02-13 8:06 ` Pekka Enberg 2013-02-13 8:16 ` Cyrill Gorcunov 1 sibling, 1 reply; 7+ messages in thread From: Pekka Enberg @ 2013-02-13 8:06 UTC (permalink / raw) To: H. Peter Anvin Cc: Borislav Petkov, mingo, linux-kernel, boris.ostrovsky, tglx, hpa, linux-tip-commits, Cyrill Gorcunov, Sasha Levin, Asias He On Wed, Feb 13, 2013 at 2:21 AM, H. Peter Anvin <hpa@zytor.com> wrote: >>> + rdmsrl(MSR_AMD64_BU_CFG2, value); >>> + value &= ~(1ULL << 24); >>> + wrmsrl(MSR_AMD64_BU_CFG2, value); >>> + } >>> } >>> >>> rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); >> >> >> However, the more serious issue is that that same kernel #GPs when >> booted in kvm. It seems it cannot stomach that specific MSR, see the >> second "<-- trapping instruction" below and that BU_CFG2 MSR landing in >> %ecx in the line before that. >> >> Oh, and this happens only with the kvm executable (/usr/bin/kvm) in >> debian testing. If I use qemu from git, it passes over init_amd just >> fine. >> >> Hmmm.. > > It #GPs on an MSR, which tends to be a bug in the VMM; RDMSR/WRMSR generally > kick out to the VMM. There isn't a huge lot of work we can do about that... > > I think Qemu defaults to ignoring unknown-to-it MSRs whereas maybe kvmtool > croaks? Pekka? I think we should also be fine. Cyrillos? ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [tip:x86/cpu] x86, AMD: Enable WC+ memory type on family 10 processors 2013-02-13 8:06 ` Pekka Enberg @ 2013-02-13 8:16 ` Cyrill Gorcunov 0 siblings, 0 replies; 7+ messages in thread From: Cyrill Gorcunov @ 2013-02-13 8:16 UTC (permalink / raw) To: Pekka Enberg Cc: H. Peter Anvin, Borislav Petkov, mingo, linux-kernel, boris.ostrovsky, tglx, hpa, linux-tip-commits, Sasha Levin, Asias He On Wed, Feb 13, 2013 at 10:06:25AM +0200, Pekka Enberg wrote: > On Wed, Feb 13, 2013 at 2:21 AM, H. Peter Anvin <hpa@zytor.com> wrote: > >>> + rdmsrl(MSR_AMD64_BU_CFG2, value); > >>> + value &= ~(1ULL << 24); > >>> + wrmsrl(MSR_AMD64_BU_CFG2, value); > >>> + } > >>> } > >>> > >>> rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); > >> > >> > >> However, the more serious issue is that that same kernel #GPs when > >> booted in kvm. It seems it cannot stomach that specific MSR, see the > >> second "<-- trapping instruction" below and that BU_CFG2 MSR landing in > >> %ecx in the line before that. > >> > >> Oh, and this happens only with the kvm executable (/usr/bin/kvm) in > >> debian testing. If I use qemu from git, it passes over init_amd just > >> fine. > >> > >> Hmmm.. > > > > It #GPs on an MSR, which tends to be a bug in the VMM; RDMSR/WRMSR generally > > kick out to the VMM. There isn't a huge lot of work we can do about that... > > > > I think Qemu defaults to ignoring unknown-to-it MSRs whereas maybe kvmtool > > croaks? Pekka? > > I think we should also be fine. Cyrill? Never was #gp on unknown msr register access, so I think we're safe. But maybe Borislav may give lkvm a shot just to be sure? ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2013-02-13 8:16 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2013-01-29 21:32 [PATCH 2/2] x86,AMD: Enable WC+ memory type on family 10 processors Boris Ostrovsky 2013-01-31 22:45 ` [tip:x86/cpu] x86, AMD: " tip-bot for Boris Ostrovsky 2013-02-13 0:16 ` Borislav Petkov 2013-02-13 0:21 ` H. Peter Anvin 2013-02-13 0:31 ` Borislav Petkov 2013-02-13 8:06 ` Pekka Enberg 2013-02-13 8:16 ` Cyrill Gorcunov
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