[U-Boot] [PATCH 00/10] Add TI814x EVM Support

[U-Boot] [PATCH 00/10] Add TI814x EVM Support

[Matt Porter]

This series adds support for the PG1.0 TI814x EVM board. TI814x
fits into the existing AM33XX SoC support with some refactoring
of the AM33XX-specific emif4, clock, and mux code.

It has been tested booting up a Linux kernel and regression tested
on BeagleBone and EVM-SK AM33XX boards.

Matt Porter (10):
  am33xx: convert defines from am33xx-specific to generic names
  am33xx: refactor emif4/ddr to support multiple EMIF instances
  am33xx: refactor am33xx clocks and add ti814x support
  am33xx: refactor am33xx mux support and add ti814x support
  am33xx: add ti814x specific register definitions
  am33xx: add dmm support to emif4 library
  ti814x_evm: add ti814x evm board support
  ns16550: enable quirks for ti814x
  ti814x_evm: enable ti814x evm build
  MAINTAINERS: add ti814x_evm maintainer

 MAINTAINERS                                      |    4 +
 Makefile                                         |    2 +-
 arch/arm/cpu/armv7/Makefile                      |    2 +-
 arch/arm/cpu/armv7/am33xx/Makefile               |    3 +-
 arch/arm/cpu/armv7/am33xx/board.c                |    4 +-
 arch/arm/cpu/armv7/am33xx/clock-am335x.c         |  374 ++++++++++++++++++++++
 arch/arm/cpu/armv7/am33xx/clock-ti814x.c         |  234 ++++++++++++++
 arch/arm/cpu/armv7/am33xx/clock.c                |  374 ----------------------
 arch/arm/cpu/armv7/am33xx/ddr.c                  |   99 +++---
 arch/arm/cpu/armv7/am33xx/emif4.c                |   55 ++--
 arch/arm/cpu/armv7/am33xx/sys_info.c             |    3 +
 arch/arm/cpu/armv7/omap-common/Makefile          |    2 +-
 arch/arm/include/asm/arch-am33xx/clock.h         |    4 +
 arch/arm/include/asm/arch-am33xx/clocks_ti814x.h |  112 +++++++
 arch/arm/include/asm/arch-am33xx/cpu.h           |   11 +-
 arch/arm/include/asm/arch-am33xx/ddr_defs.h      |   57 +++-
 arch/arm/include/asm/arch-am33xx/hardware.h      |   60 +++-
 arch/arm/include/asm/arch-am33xx/mux-am335x.h    |  246 ++++++++++++++
 arch/arm/include/asm/arch-am33xx/mux-ti814x.h    |  310 ++++++++++++++++++
 arch/arm/include/asm/arch-am33xx/mux.h           |  230 +------------
 arch/arm/include/asm/arch-am33xx/omap.h          |    7 +
 arch/arm/include/asm/arch-am33xx/spl.h           |    5 +
 board/ti/am335x/board.c                          |   10 +-
 board/ti/ti814x/Makefile                         |   46 +++
 board/ti/ti814x/evm.c                            |  198 ++++++++++++
 board/ti/ti814x/evm.h                            |    7 +
 board/ti/ti814x/mux.c                            |   51 +++
 boards.cfg                                       |    1 +
 drivers/serial/ns16550.c                         |    5 +-
 include/configs/ti814x_evm.h                     |  213 ++++++++++++
 spl/Makefile                                     |    2 +-
 31 files changed, 2044 insertions(+), 687 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/am33xx/clock-am335x.c
 create mode 100644 arch/arm/cpu/armv7/am33xx/clock-ti814x.c
 delete mode 100644 arch/arm/cpu/armv7/am33xx/clock.c
 create mode 100644 arch/arm/include/asm/arch-am33xx/clocks_ti814x.h
 create mode 100644 arch/arm/include/asm/arch-am33xx/mux-am335x.h
 create mode 100644 arch/arm/include/asm/arch-am33xx/mux-ti814x.h
 create mode 100644 board/ti/ti814x/Makefile
 create mode 100644 board/ti/ti814x/evm.c
 create mode 100644 board/ti/ti814x/evm.h
 create mode 100644 board/ti/ti814x/mux.c
 create mode 100644 include/configs/ti814x_evm.h

-- 
1.7.9.5

[U-Boot] [PATCH 01/10] am33xx: convert defines from am33xx-specific to generic names

[Matt Porter]

Eliminate AM33xx specific names to prepare for TI814x support
within AM33xx-land.

Signed-off-by: Matt Porter <mporter@ti.com>
---
 arch/arm/cpu/armv7/am33xx/board.c           |    4 ++--
 arch/arm/include/asm/arch-am33xx/hardware.h |   10 +++++-----
 board/ti/am335x/board.c                     |    6 +++---
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index ab31326..b186b32 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -141,11 +141,11 @@ int arch_misc_init(void)
 {
 #ifdef CONFIG_AM335X_USB0
 	musb_register(&otg0_plat, &otg0_board_data,
-		(void *)AM335X_USB0_OTG_BASE);
+		(void *)USB0_OTG_BASE);
 #endif
 #ifdef CONFIG_AM335X_USB1
 	musb_register(&otg1_plat, &otg1_board_data,
-		(void *)AM335X_USB1_OTG_BASE);
+		(void *)USB1_OTG_BASE);
 #endif
 	return 0;
 }
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
index 6dd3296..7016e25 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -84,14 +84,14 @@
 #define GPMC_BASE			0x50000000
 
 /* CPSW Config space */
-#define AM335X_CPSW_BASE		0x4A100000
-#define AM335X_CPSW_MDIO_BASE		0x4A101000
+#define CPSW_BASE			0x4A100000
+#define CPSW_MDIO_BASE			0x4A101000
 
 /* RTC base address */
-#define AM335X_RTC_BASE			0x44E3E000
+#define RTC_BASE			0x44E3E000
 
 /* OTG */
-#define AM335X_USB0_OTG_BASE		0x47401000
-#define AM335X_USB1_OTG_BASE		0x47401800
+#define USB0_OTG_BASE			0x47401000
+#define USB1_OTG_BASE			0x47401800
 
 #endif /* __AM33XX_HARDWARE_H */
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index ed4229e..1e698df 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -123,7 +123,7 @@ static int read_eeprom(void)
 
 static void rtc32k_enable(void)
 {
-	struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE;
+	struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
 
 	/*
 	 * Unlock the RTC's registers.  For more details please see the
@@ -365,8 +365,8 @@ static struct cpsw_slave_data cpsw_slaves[] = {
 };
 
 static struct cpsw_platform_data cpsw_data = {
-	.mdio_base		= AM335X_CPSW_MDIO_BASE,
-	.cpsw_base		= AM335X_CPSW_BASE,
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
 	.mdio_div		= 0xff,
 	.channels		= 8,
 	.cpdma_reg_ofs		= 0x800,
-- 
1.7.9.5

[U-Boot] [PATCH 02/10] am33xx: refactor emif4/ddr to support multiple EMIF instances

[Matt Porter]

The AM33xx emif4/ddr support closely matches what is need to support
TI814x except that TI814x has two EMIF instances. Refactor all the
emif4 helper calls and the config_ddr() init function to use an
additional instance number argument.

Signed-off-by: Matt Porter <mporter@ti.com>
---
 arch/arm/cpu/armv7/am33xx/ddr.c             |   99 ++++++++++++++++-----------
 arch/arm/cpu/armv7/am33xx/emif4.c           |   38 +++++-----
 arch/arm/include/asm/arch-am33xx/ddr_defs.h |   52 ++++++++++++--
 arch/arm/include/asm/arch-am33xx/hardware.h |   18 ++++-
 board/ti/am335x/board.c                     |    4 +-
 5 files changed, 143 insertions(+), 68 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index fd9fc4a..493b99b 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -24,15 +24,20 @@ http://www.ti.com/
 /**
  * Base address for EMIF instances
  */
-static struct emif_reg_struct *emif_reg = {
-				(struct emif_reg_struct *)EMIF4_0_CFG_BASE};
+static struct emif_reg_struct *emif_reg[2] = {
+				(struct emif_reg_struct *)EMIF4_0_CFG_BASE,
+				(struct emif_reg_struct *)EMIF4_1_CFG_BASE};
 
 /**
- * Base address for DDR instance
+ * Base addresses for DDR PHY cmd/data regs
  */
-static struct ddr_regs *ddr_reg[2] = {
-				(struct ddr_regs *)DDR_PHY_BASE_ADDR,
-				(struct ddr_regs *)DDR_PHY_BASE_ADDR2};
+static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
+				(struct ddr_regs *)DDR_PHY_CMD_ADDR,
+				(struct ddr_regs *)DDR_PHY_CMD_ADDR2};
+
+static struct ddr_data_regs *ddr_data_reg[2] = {
+				(struct ddr_regs *)DDR_PHY_DATA_ADDR,
+				(struct ddr_regs *)DDR_PHY_DATA_ADDR2};
 
 /**
  * Base address for ddr io control instances
@@ -43,70 +48,84 @@ static struct ddr_cmdtctrl *ioctrl_reg = {
 /**
  * Configure SDRAM
  */
-void config_sdram(const struct emif_regs *regs)
+void config_sdram(const struct emif_regs *regs, int nr)
 {
-	writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
-	writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
+	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
+	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 	if (regs->zq_config){
-		writel(regs->zq_config, &emif_reg->emif_zq_config);
+		writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
 		writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
 	}
-	writel(regs->sdram_config, &emif_reg->emif_sdram_config);
+	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 }
 
 /**
  * Set SDRAM timings
  */
-void set_sdram_timings(const struct emif_regs *regs)
+void set_sdram_timings(const struct emif_regs *regs, int nr)
 {
-	writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1);
-	writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1_shdw);
-	writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2);
-	writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2_shdw);
-	writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3);
-	writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3_shdw);
+	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
+	writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
+	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
+	writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
+	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
+	writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
 }
 
 /**
  * Configure DDR PHY
  */
-void config_ddr_phy(const struct emif_regs *regs)
+void config_ddr_phy(const struct emif_regs *regs, int nr)
 {
-	writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1);
-	writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1_shdw);
+	writel(regs->emif_ddr_phy_ctlr_1,
+		&emif_reg[nr]->emif_ddr_phy_ctrl_1);
+	writel(regs->emif_ddr_phy_ctlr_1,
+		&emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
 }
 
 /**
  * Configure DDR CMD control registers
  */
-void config_cmd_ctrl(const struct cmd_control *cmd)
+void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
 {
-	writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
-	writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff);
-	writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout);
+	writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
+	writel(cmd->cmd0dldiff, &ddr_cmd_reg[nr]->cm0dldiff);
+	writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
 
-	writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio);
-	writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff);
-	writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout);
+	writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
+	writel(cmd->cmd1dldiff, &ddr_cmd_reg[nr]->cm1dldiff);
+	writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
 
-	writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio);
-	writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
-	writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
+	writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
+	writel(cmd->cmd2dldiff, &ddr_cmd_reg[nr]->cm2dldiff);
+	writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
 }
 
 /**
  * Configure DDR DATA registers
  */
-void config_ddr_data(int macrono, const struct ddr_data *data)
+void config_ddr_data(const struct ddr_data *data, int nr)
 {
-	writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0);
-	writel(data->datawdsratio0, &ddr_reg[macrono]->dt0wdsratio0);
-	writel(data->datawiratio0, &ddr_reg[macrono]->dt0wiratio0);
-	writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0);
-	writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0);
-	writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0);
-	writel(data->datauserank0delay, &ddr_reg[macrono]->dt0rdelays0);
-	writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
+	int i;
+
+	for (i = 0; i < DDR_DATA_REGS_NR; i++) {
+		writel(data->datardsratio0,
+			&(ddr_data_reg[nr]+i)->dt0rdsratio0);
+		writel(data->datawdsratio0,
+			&(ddr_data_reg[nr]+i)->dt0wdsratio0);
+		writel(data->datawiratio0,
+			&(ddr_data_reg[nr]+i)->dt0wiratio0);
+		writel(data->datagiratio0,
+			&(ddr_data_reg[nr]+i)->dt0giratio0);
+		writel(data->datafwsratio0,
+			&(ddr_data_reg[nr]+i)->dt0fwsratio0);
+		writel(data->datawrsratio0,
+			&(ddr_data_reg[nr]+i)->dt0wrsratio0);
+		writel(data->datauserank0delay,
+			&(ddr_data_reg[nr]+i)->dt0rdelays0);
+		writel(data->datadldiff0,
+			&(ddr_data_reg[nr]+i)->dt0dldiff0);
+	}
 }
 
 void config_io_ctrl(unsigned long val)
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 01e3a52..0c617fa 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -44,44 +44,46 @@ void dram_init_banksize(void)
 
 
 #ifdef CONFIG_SPL_BUILD
-static struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
+static struct vtp_reg *vtpreg[2] = {
+				(struct vtp_reg *)VTP0_CTRL_ADDR,
+				(struct vtp_reg *)VTP1_CTRL_ADDR};
 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
 
-static void config_vtp(void)
+static void config_vtp(int nr)
 {
-	writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
-			&vtpreg->vtp0ctrlreg);
-	writel(readl(&vtpreg->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
-			&vtpreg->vtp0ctrlreg);
-	writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_START_EN,
-			&vtpreg->vtp0ctrlreg);
+	writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
+			&vtpreg[nr]->vtp0ctrlreg);
+	writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
+			&vtpreg[nr]->vtp0ctrlreg);
+	writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
+			&vtpreg[nr]->vtp0ctrlreg);
 
 	/* Poll for READY */
-	while ((readl(&vtpreg->vtp0ctrlreg) & VTP_CTRL_READY) !=
+	while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
 			VTP_CTRL_READY)
 		;
 }
 
 void config_ddr(unsigned int pll, unsigned int ioctrl,
 		const struct ddr_data *data, const struct cmd_control *ctrl,
-		const struct emif_regs *regs)
+		const struct emif_regs *regs, int nr)
 {
 	enable_emif_clocks();
 	ddr_pll_config(pll);
-	config_vtp();
-	config_cmd_ctrl(ctrl);
-
-	config_ddr_data(0, data);
-	config_ddr_data(1, data);
+	config_vtp(nr);
+	config_cmd_ctrl(ctrl, nr);
 
+	config_ddr_data(data, nr);
+#ifdef CONFIG_AM33XX
 	config_io_ctrl(ioctrl);
 
 	/* Set CKE to be controlled by EMIF/DDR PHY */
 	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
+#endif
 
 	/* Program EMIF instance */
-	config_ddr_phy(regs);
-	set_sdram_timings(regs);
-	config_sdram(regs);
+	config_ddr_phy(regs, nr);
+	set_sdram_timings(regs, nr);
+	config_sdram(regs, nr);
 }
 #endif
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 8e69fb6..8bf25a0 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -68,17 +68,57 @@
 /**
  * Configure SDRAM
  */
-void config_sdram(const struct emif_regs *regs);
+void config_sdram(const struct emif_regs *regs, int nr);
 
 /**
  * Set SDRAM timings
  */
-void set_sdram_timings(const struct emif_regs *regs);
+void set_sdram_timings(const struct emif_regs *regs, int nr);
 
 /**
  * Configure DDR PHY
  */
-void config_ddr_phy(const struct emif_regs *regs);
+void config_ddr_phy(const struct emif_regs *regs, int nr);
+
+struct ddr_cmd_regs {
+	unsigned int resv0[7];
+	unsigned int cm0csratio;	/* offset 0x01C */
+	unsigned int resv1[2];
+	unsigned int cm0dldiff;		/* offset 0x028 */
+	unsigned int cm0iclkout;	/* offset 0x02C */
+	unsigned int resv2[8];
+	unsigned int cm1csratio;	/* offset 0x050 */
+	unsigned int resv3[2];
+	unsigned int cm1dldiff;		/* offset 0x05C */
+	unsigned int cm1iclkout;	/* offset 0x060 */
+	unsigned int resv4[8];
+	unsigned int cm2csratio;	/* offset 0x084 */
+	unsigned int resv5[2];
+	unsigned int cm2dldiff;		/* offset 0x090 */
+	unsigned int cm2iclkout;	/* offset 0x094 */
+	unsigned int resv6[3];
+};
+
+struct ddr_data_regs {
+	unsigned int dt0rdsratio0;	/* offset 0x0C8 */
+	unsigned int resv1[4];
+	unsigned int dt0wdsratio0;	/* offset 0x0DC */
+	unsigned int resv2[4];
+	unsigned int dt0wiratio0;	/* offset 0x0F0 */
+	unsigned int resv3;
+	unsigned int dt0wimode0;	/* offset 0x0F8 */
+	unsigned int dt0giratio0;	/* offset 0x0FC */
+	unsigned int resv4;
+	unsigned int dt0gimode0;	/* offset 0x104 */
+	unsigned int dt0fwsratio0;	/* offset 0x108 */
+	unsigned int resv5[4];
+	unsigned int dt0dqoffset;	/* offset 0x11C */
+	unsigned int dt0wrsratio0;	/* offset 0x120 */
+	unsigned int resv6[4];
+	unsigned int dt0rdelays0;	/* offset 0x134 */
+	unsigned int dt0dldiff0;	/* offset 0x138 */
+	unsigned int resv7[12];
+};
 
 /**
  * This structure represents the DDR registers on AM33XX devices.
@@ -159,12 +199,12 @@ struct ddr_data {
 /**
  * Configure DDR CMD control registers
  */
-void config_cmd_ctrl(const struct cmd_control *cmd);
+void config_cmd_ctrl(const struct cmd_control *cmd, int nr);
 
 /**
  * Configure DDR DATA registers
  */
-void config_ddr_data(int data_macrono, const struct ddr_data *data);
+void config_ddr_data(const struct ddr_data *data, int nr);
 
 /**
  * This structure represents the DDR io control on AM33XX devices.
@@ -192,6 +232,6 @@ struct ddr_ctrl {
 
 void config_ddr(unsigned int pll, unsigned int ioctrl,
 		const struct ddr_data *data, const struct cmd_control *ctrl,
-		const struct emif_regs *regs);
+		const struct emif_regs *regs, int nr);
 
 #endif  /* _DDR_DEFS_H */
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
index 7016e25..41ab2c0 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -66,13 +66,27 @@
 #define PRM_DEVICE			0x44E00F00
 
 /* VTP Base address */
+#ifdef CONFIG_AM33XX
 #define VTP0_CTRL_ADDR			0x44E10E0C
+#elif defined(CONFIG_TI814X)
+#define VTP0_CTRL_ADDR			0x48140E0C
+#endif
+#define VTP1_CTRL_ADDR			0x48140E10
 
 /* DDR Base address */
 #define DDR_CTRL_ADDR			0x44E10E04
 #define DDR_CONTROL_BASE_ADDR		0x44E11404
-#define DDR_PHY_BASE_ADDR		0x44E12000
-#define DDR_PHY_BASE_ADDR2		0x44E120A4
+#ifdef CONFIG_AM33XX
+#define DDR_PHY_CMD_ADDR		0x44E12000
+#define DDR_PHY_DATA_ADDR		0x44E120C8
+#define DDR_DATA_REGS_NR		2
+#elif defined(CONFIG_TI814X)
+#define DDR_PHY_CMD_ADDR		0x47C0C400
+#define DDR_PHY_DATA_ADDR		0x47C0C4C8
+#define DDR_DATA_REGS_NR		4
+#endif
+#define DDR_PHY_CMD_ADDR2		0x47C0C800
+#define DDR_PHY_DATA_ADDR2		0x47C0C8C8
 
 /* UART */
 #define DEFAULT_UART_BASE		UART0_BASE
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 1e698df..3189408 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -300,10 +300,10 @@ void s_init(void)
 
 	if (board_is_evm_sk() || board_is_bone_lt())
 		config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
-			   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
+			   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 	else
 		config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
-			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data);
+			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 #endif
 }
 
-- 
1.7.9.5

[U-Boot] [PATCH 03/10] am33xx: refactor am33xx clocks and add ti814x support

[Matt Porter]

Split clock.c for am335x and ti814x and add the ti814x include file.

Signed-off-by: Matt Porter <mporter@ti.com>
---
 arch/arm/cpu/armv7/am33xx/Makefile               |    3 +-
 arch/arm/cpu/armv7/am33xx/clock-am335x.c         |  374 ++++++++++++++++++++++
 arch/arm/cpu/armv7/am33xx/clock-ti814x.c         |  234 ++++++++++++++
 arch/arm/cpu/armv7/am33xx/clock.c                |  374 ----------------------
 arch/arm/include/asm/arch-am33xx/clock.h         |    4 +
 arch/arm/include/asm/arch-am33xx/clocks_ti814x.h |  112 +++++++
 6 files changed, 726 insertions(+), 375 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/am33xx/clock-am335x.c
 create mode 100644 arch/arm/cpu/armv7/am33xx/clock-ti814x.c
 delete mode 100644 arch/arm/cpu/armv7/am33xx/clock.c
 create mode 100644 arch/arm/include/asm/arch-am33xx/clocks_ti814x.h

diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile
index 70c443e..7051029 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -16,7 +16,8 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).o
 
-COBJS	+= clock.o
+COBJS-$(CONFIG_AM33XX)	+= clock-am335x.o
+COBJS-$(CONFIG_TI814X)	+= clock-ti814x.o
 COBJS	+= sys_info.o
 COBJS	+= mem.o
 COBJS	+= ddr.o
diff --git a/arch/arm/cpu/armv7/am33xx/clock-am335x.c b/arch/arm/cpu/armv7/am33xx/clock-am335x.c
new file mode 100644
index 0000000..d7d98d1
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/clock-am335x.c
@@ -0,0 +1,374 @@
+/*
+ * clock.c
+ *
+ * clocks for AM33XX based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+#define PRCM_MOD_EN		0x2
+#define PRCM_FORCE_WAKEUP	0x2
+#define PRCM_FUNCTL		0x0
+
+#define PRCM_EMIF_CLK_ACTIVITY	BIT(2)
+#define PRCM_L3_GCLK_ACTIVITY	BIT(4)
+
+#define PLL_BYPASS_MODE		0x4
+#define ST_MN_BYPASS		0x00000100
+#define ST_DPLL_CLK		0x00000001
+#define CLK_SEL_MASK		0x7ffff
+#define CLK_DIV_MASK		0x1f
+#define CLK_DIV2_MASK		0x7f
+#define CLK_SEL_SHIFT		0x8
+#define CLK_MODE_SEL		0x7
+#define CLK_MODE_MASK		0xfffffff8
+#define CLK_DIV_SEL		0xFFFFFFE0
+#define CPGMAC0_IDLE		0x30000
+#define DPLL_CLKDCOLDO_GATE_CTRL        0x300
+
+const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
+const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
+const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
+const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
+
+static void enable_interface_clocks(void)
+{
+	/* Enable all the Interconnect Modules */
+	writel(PRCM_MOD_EN, &cmper->l3clkctrl);
+	while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN)
+		;
+
+	writel(PRCM_MOD_EN, &cmper->l4lsclkctrl);
+	while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN)
+		;
+
+	writel(PRCM_MOD_EN, &cmper->l4fwclkctrl);
+	while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN)
+		;
+
+	writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl);
+	while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN)
+		;
+
+	writel(PRCM_MOD_EN, &cmper->l3instrclkctrl);
+	while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN)
+		;
+
+	writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
+	while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
+		;
+
+	writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl);
+	while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN)
+		;
+}
+
+/*
+ * Force power domain wake up transition
+ * Ensure that the corresponding interface clock is active before
+ * using the peripheral
+ */
+static void power_domain_wkup_transition(void)
+{
+	writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl);
+	writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl);
+	writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl);
+	writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl);
+	writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl);
+}
+
+/*
+ * Enable the peripheral clock for required peripherals
+ */
+static void enable_per_clocks(void)
+{
+	/* Enable the control module though RBL would have done it*/
+	writel(PRCM_MOD_EN, &cmwkup->wkctrlclkctrl);
+	while (readl(&cmwkup->wkctrlclkctrl) != PRCM_MOD_EN)
+		;
+
+	/* Enable the module clock */
+	writel(PRCM_MOD_EN, &cmper->timer2clkctrl);
+	while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
+		;
+
+	/* Select the Master osc 24 MHZ as Timer2 clock source */
+	writel(0x1, &cmdpll->clktimer2clk);
+
+	/* UART0 */
+	writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
+	while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
+		;
+
+	/* UART1 */
+#ifdef CONFIG_SERIAL2
+	writel(PRCM_MOD_EN, &cmper->uart1clkctrl);
+	while (readl(&cmper->uart1clkctrl) != PRCM_MOD_EN)
+		;
+#endif /* CONFIG_SERIAL2 */
+
+	/* UART2 */
+#ifdef CONFIG_SERIAL3
+	writel(PRCM_MOD_EN, &cmper->uart2clkctrl);
+	while (readl(&cmper->uart2clkctrl) != PRCM_MOD_EN)
+		;
+#endif /* CONFIG_SERIAL3 */
+
+	/* UART3 */
+#ifdef CONFIG_SERIAL4
+	writel(PRCM_MOD_EN, &cmper->uart3clkctrl);
+	while (readl(&cmper->uart3clkctrl) != PRCM_MOD_EN)
+		;
+#endif /* CONFIG_SERIAL4 */
+
+	/* UART4 */
+#ifdef CONFIG_SERIAL5
+	writel(PRCM_MOD_EN, &cmper->uart4clkctrl);
+	while (readl(&cmper->uart4clkctrl) != PRCM_MOD_EN)
+		;
+#endif /* CONFIG_SERIAL5 */
+
+	/* UART5 */
+#ifdef CONFIG_SERIAL6
+	writel(PRCM_MOD_EN, &cmper->uart5clkctrl);
+	while (readl(&cmper->uart5clkctrl) != PRCM_MOD_EN)
+		;
+#endif /* CONFIG_SERIAL6 */
+
+	/* GPMC */
+	writel(PRCM_MOD_EN, &cmper->gpmcclkctrl);
+	while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN)
+		;
+
+	/* ELM */
+	writel(PRCM_MOD_EN, &cmper->elmclkctrl);
+	while (readl(&cmper->elmclkctrl) != PRCM_MOD_EN)
+		;
+
+	/* MMC0*/
+	writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
+	while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
+		;
+
+	/* i2c0 */
+	writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
+	while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)
+		;
+
+	/* gpio1 module */
+	writel(PRCM_MOD_EN, &cmper->gpio1clkctrl);
+	while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN)
+		;
+
+	/* gpio2 module */
+	writel(PRCM_MOD_EN, &cmper->gpio2clkctrl);
+	while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN)
+		;
+
+	/* gpio3 module */
+	writel(PRCM_MOD_EN, &cmper->gpio3clkctrl);
+	while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN)
+		;
+
+	/* i2c1 */
+	writel(PRCM_MOD_EN, &cmper->i2c1clkctrl);
+	while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN)
+		;
+
+	/* Ethernet */
+	writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
+	while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
+		;
+
+	/* spi0 */
+	writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
+	while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
+		;
+
+	/* RTC */
+	writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
+	while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
+		;
+
+	/* MUSB */
+	writel(PRCM_MOD_EN, &cmper->usb0clkctrl);
+	while (readl(&cmper->usb0clkctrl) != PRCM_MOD_EN)
+		;
+}
+
+static void mpu_pll_config(void)
+{
+	u32 clkmode, clksel, div_m2;
+
+	clkmode = readl(&cmwkup->clkmoddpllmpu);
+	clksel = readl(&cmwkup->clkseldpllmpu);
+	div_m2 = readl(&cmwkup->divm2dpllmpu);
+
+	/* Set the PLL to bypass Mode */
+	writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu);
+	while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS)
+		;
+
+	clksel = clksel & (~CLK_SEL_MASK);
+	clksel = clksel | ((MPUPLL_M << CLK_SEL_SHIFT) | MPUPLL_N);
+	writel(clksel, &cmwkup->clkseldpllmpu);
+
+	div_m2 = div_m2 & ~CLK_DIV_MASK;
+	div_m2 = div_m2 | MPUPLL_M2;
+	writel(div_m2, &cmwkup->divm2dpllmpu);
+
+	clkmode = clkmode | CLK_MODE_SEL;
+	writel(clkmode, &cmwkup->clkmoddpllmpu);
+
+	while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK)
+		;
+}
+
+static void core_pll_config(void)
+{
+	u32 clkmode, clksel, div_m4, div_m5, div_m6;
+
+	clkmode = readl(&cmwkup->clkmoddpllcore);
+	clksel = readl(&cmwkup->clkseldpllcore);
+	div_m4 = readl(&cmwkup->divm4dpllcore);
+	div_m5 = readl(&cmwkup->divm5dpllcore);
+	div_m6 = readl(&cmwkup->divm6dpllcore);
+
+	/* Set the PLL to bypass Mode */
+	writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
+
+	while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
+		;
+
+	clksel = clksel & (~CLK_SEL_MASK);
+	clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
+	writel(clksel, &cmwkup->clkseldpllcore);
+
+	div_m4 = div_m4 & ~CLK_DIV_MASK;
+	div_m4 = div_m4 | COREPLL_M4;
+	writel(div_m4, &cmwkup->divm4dpllcore);
+
+	div_m5 = div_m5 & ~CLK_DIV_MASK;
+	div_m5 = div_m5 | COREPLL_M5;
+	writel(div_m5, &cmwkup->divm5dpllcore);
+
+	div_m6 = div_m6 & ~CLK_DIV_MASK;
+	div_m6 = div_m6 | COREPLL_M6;
+	writel(div_m6, &cmwkup->divm6dpllcore);
+
+	clkmode = clkmode | CLK_MODE_SEL;
+	writel(clkmode, &cmwkup->clkmoddpllcore);
+
+	while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
+		;
+}
+
+static void per_pll_config(void)
+{
+	u32 clkmode, clksel, div_m2;
+
+	clkmode = readl(&cmwkup->clkmoddpllper);
+	clksel = readl(&cmwkup->clkseldpllper);
+	div_m2 = readl(&cmwkup->divm2dpllper);
+
+	/* Set the PLL to bypass Mode */
+	writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllper);
+
+	while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS)
+		;
+
+	clksel = clksel & (~CLK_SEL_MASK);
+	clksel = clksel | ((PERPLL_M << CLK_SEL_SHIFT) | PERPLL_N);
+	writel(clksel, &cmwkup->clkseldpllper);
+
+	div_m2 = div_m2 & ~CLK_DIV2_MASK;
+	div_m2 = div_m2 | PERPLL_M2;
+	writel(div_m2, &cmwkup->divm2dpllper);
+
+	clkmode = clkmode | CLK_MODE_SEL;
+	writel(clkmode, &cmwkup->clkmoddpllper);
+
+	while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
+		;
+
+	writel(DPLL_CLKDCOLDO_GATE_CTRL, &cmwkup->clkdcoldodpllper);
+}
+
+void ddr_pll_config(unsigned int ddrpll_m)
+{
+	u32 clkmode, clksel, div_m2;
+
+	clkmode = readl(&cmwkup->clkmoddpllddr);
+	clksel = readl(&cmwkup->clkseldpllddr);
+	div_m2 = readl(&cmwkup->divm2dpllddr);
+
+	/* Set the PLL to bypass Mode */
+	clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE;
+	writel(clkmode, &cmwkup->clkmoddpllddr);
+
+	/* Wait till bypass mode is enabled */
+	while ((readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS)
+				!= ST_MN_BYPASS)
+		;
+
+	clksel = clksel & (~CLK_SEL_MASK);
+	clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N);
+	writel(clksel, &cmwkup->clkseldpllddr);
+
+	div_m2 = div_m2 & CLK_DIV_SEL;
+	div_m2 = div_m2 | DDRPLL_M2;
+	writel(div_m2, &cmwkup->divm2dpllddr);
+
+	clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL;
+	writel(clkmode, &cmwkup->clkmoddpllddr);
+
+	/* Wait till dpll is locked */
+	while ((readl(&cmwkup->idlestdpllddr) & ST_DPLL_CLK) != ST_DPLL_CLK)
+		;
+}
+
+void enable_emif_clocks(void)
+{
+	/* Enable the  EMIF_FW Functional clock */
+	writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
+	/* Enable EMIF0 Clock */
+	writel(PRCM_MOD_EN, &cmper->emifclkctrl);
+	/* Poll if module is functional */
+	while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
+		;
+}
+
+/*
+ * Configure the PLL/PRCM for necessary peripherals
+ */
+void pll_init()
+{
+	mpu_pll_config();
+	core_pll_config();
+	per_pll_config();
+
+	/* Enable the required interconnect clocks */
+	enable_interface_clocks();
+
+	/* Power domain wake up transition */
+	power_domain_wkup_transition();
+
+	/* Enable the required peripherals */
+	enable_per_clocks();
+}
diff --git a/arch/arm/cpu/armv7/am33xx/clock-ti814x.c b/arch/arm/cpu/armv7/am33xx/clock-ti814x.c
new file mode 100644
index 0000000..2b63e84
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/clock-ti814x.c
@@ -0,0 +1,234 @@
+/*
+ * clock.c
+ *
+ * clocks for TI814X based boards
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+/*
+ * Enable the peripheral clock for required peripherals
+ */
+static void enable_per_clocks(void)
+{
+	u32 temp;
+
+	/* Selects OSC0 (20MHz) for DMTIMER1 */
+	temp = readl(DMTIMER_CLKSRC);
+	temp &= ~(0x7 << 3);
+	temp |= (0x4 << 3);
+	writel(temp, DMTIMER_CLKSRC);
+
+	writel(0x2, DM_TIMER1_BASE + 0x54);
+	while (readl(DM_TIMER1_BASE + 0x10) & 1)
+		;
+
+	writel(0x1, DM_TIMER1_BASE + 0x38);
+
+	/* UARTs */
+	writel(0x2, CM_ALWON_UART_0_CLKCTRL);
+	while (readl(CM_ALWON_UART_0_CLKCTRL) != 0x2)
+		;
+
+	/* HSMMC */
+	writel(0x2, CM_ALWON_HSMMC_CLKCTRL);
+	while (readl(CM_ALWON_HSMMC_CLKCTRL) != 0x2)
+		;
+}
+
+/*
+ * select the HS1 or HS2 for DCO Freq
+ * return : CLKCTRL
+ */
+static u32 pll_dco_freq_sel(u32 clkout_dco)
+{
+	if (clkout_dco >= DCO_HS2_MIN && clkout_dco < DCO_HS2_MAX)
+		return SELFREQDCO_HS2;
+	else if (clkout_dco >= DCO_HS1_MIN && clkout_dco < DCO_HS1_MAX)
+		return SELFREQDCO_HS1;
+	else
+		return -1;
+
+}
+
+/*
+ * select the sigma delta config
+ * return: sigma delta val
+ */
+static u32 pll_sigma_delta_val(u32 clkout_dco)
+{
+	u32 sig_val = 0;
+	float frac_div;
+
+	frac_div = (float) clkout_dco / 250;
+	frac_div = frac_div + 0.90;
+	sig_val = (int)frac_div;
+	sig_val = sig_val << 24;
+
+	return sig_val;
+}
+
+/*
+ * configure individual ADPLLJ
+ */
+static void pll_config(u32 base, u32 n, u32 m, u32 m2,
+		       u32 clkctrl_val, int adpllj)
+{
+	u32 m2nval, mn2val, read_clkctrl = 0, clkout_dco = 0;
+	u32 sig_val = 0, hs_mod = 0;
+
+	m2nval = (m2 << 16) | n;
+	mn2val = m;
+
+	/* calculate clkout_dco */
+	clkout_dco = ((OSC_0_FREQ / (n+1)) * m);
+
+	/* sigma delta & Hs mode selection skip for ADPLLS*/
+	if (adpllj) {
+		sig_val = pll_sigma_delta_val(clkout_dco);
+		hs_mod = pll_dco_freq_sel(clkout_dco);
+	}
+
+	/* by-pass pll */
+	read_clkctrl = readl(base + ADPLLJ_CLKCTRL);
+	writel((read_clkctrl | 0x00800000), (base + ADPLLJ_CLKCTRL));
+	while ((readl(base + ADPLLJ_STATUS) & 0x101) != 0x101)
+		;
+
+	/* Clear TINITZ */
+	read_clkctrl = readl(base + ADPLLJ_CLKCTRL);
+	writel((read_clkctrl & 0xfffffffe), (base + ADPLLJ_CLKCTRL));
+
+	/*
+	 * ref_clk = 20/(n + 1);
+	 * clkout_dco = ref_clk * m;
+	 * clk_out = clkout_dco/m2;
+	*/
+
+	read_clkctrl = readl(base + ADPLLJ_CLKCTRL) & 0xffffe3ff;
+	writel(m2nval, (base + ADPLLJ_M2NDIV));
+	writel(mn2val, (base + ADPLLJ_MN2DIV));
+
+	/* Skip for modena(ADPLLS) */
+	if (adpllj) {
+		writel(sig_val, (base + ADPLLJ_FRACDIV));
+		writel((read_clkctrl | hs_mod), (base + ADPLLJ_CLKCTRL));
+	}
+
+	/* Load M2, N2 dividers of ADPLL */
+	writel(0x1, (base + ADPLLJ_TENABLEDIV));
+	writel(0x0, (base + ADPLLJ_TENABLEDIV));
+
+	/* Load M, N dividers of ADPLL */
+	writel(0x1, (base + ADPLLJ_TENABLE));
+	writel(0x0, (base + ADPLLJ_TENABLE));
+
+	/* Configure CLKDCOLDOEN,CLKOUTLDOEN,CLKOUT Enable BITS */
+	read_clkctrl = readl(base + ADPLLJ_CLKCTRL) & 0xdfe5ffff;
+	if (adpllj)
+		writel((read_clkctrl | ADPLLJ_CLKCTRL_CLKDCO),
+						base + ADPLLJ_CLKCTRL);
+
+	/* Enable TINTZ and disable IDLE(PLL in Active & Locked Mode */
+	read_clkctrl = readl(base + ADPLLJ_CLKCTRL) & 0xff7fffff;
+	writel((read_clkctrl | 0x1), base + ADPLLJ_CLKCTRL);
+
+	/* Wait for phase and freq lock */
+	while ((readl(base + ADPLLJ_STATUS) & 0x600) != 0x600)
+		;
+
+}
+
+static void unlock_pll_control_mmr(void)
+{
+	/* TRM 2.10.1.4 and 3.2.7-3.2.11 */
+	writel(0x1EDA4C3D, 0x481C5040);
+	writel(0x2FF1AC2B, 0x48140060);
+	writel(0xF757FDC0, 0x48140064);
+	writel(0xE2BC3A6D, 0x48140068);
+	writel(0x1EBF131D, 0x4814006c);
+	writel(0x6F361E05, 0x48140070);
+}
+
+static void mpu_pll_config(void)
+{
+	pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0);
+}
+
+static void l3_pll_config(void)
+{
+	u32 l3_osc_src, rd_osc_src = 0;
+
+	l3_osc_src = L3_OSC_SRC;
+	rd_osc_src = readl(OSC_SRC_CTRL);
+
+	if (OSC_SRC0 == l3_osc_src)
+		writel((rd_osc_src & 0xfffffffe)|0x0, OSC_SRC_CTRL);
+	else
+		writel((rd_osc_src & 0xfffffffe)|0x1, OSC_SRC_CTRL);
+
+	pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1);
+}
+
+void ddr_pll_config(unsigned int ddrpll_m)
+{
+	pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1);
+}
+
+void enable_dmm_clocks(void)
+{
+	writel(0x2, CM_DEFAULT_FW_CLKCTRL);
+	writel(0x2, CM_DEFAULT_L3_FAST_CLKSTCTRL);
+	while ((readl(CM_DEFAULT_L3_FAST_CLKSTCTRL) & 0x300) != 0x300)
+		;
+	writel(0x2, CM_ALWON_L3_SLOW_CLKSTCTRL);
+	while ((readl(CM_ALWON_L3_SLOW_CLKSTCTRL) & 0x2100) != 0x2100)
+		;
+	writel(0x2, CM_DEFAULT_DMM_CLKCTRL);
+	while ((readl(CM_DEFAULT_DMM_CLKCTRL)) != 0x2)
+		;
+}
+
+void enable_emif_clocks(void)
+{
+	writel(0x2, CM_DEFAULT_EMIF_0_CLKCTRL);
+	while ((readl(CM_DEFAULT_EMIF_0_CLKCTRL)) != 0x2)
+		;
+	writel(0x2, CM_DEFAULT_EMIF_1_CLKCTRL);
+	while ((readl(CM_DEFAULT_EMIF_1_CLKCTRL)) != 0x2)
+		;
+}
+
+/*
+ * Configure the PLL/PRCM for necessary peripherals
+ */
+void pll_init()
+{
+	unlock_pll_control_mmr();
+
+	/* Enable the control module */
+	writel(0x2, CM_ALWON_CONTROL_CLKCTRL);
+
+	mpu_pll_config();
+
+	l3_pll_config();
+
+	/* Enable the required peripherals */
+	enable_per_clocks();
+}
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
deleted file mode 100644
index d7d98d1..0000000
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ /dev/null
@@ -1,374 +0,0 @@
-/*
- * clock.c
- *
- * clocks for AM33XX based boards
- *
- * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-#define PRCM_MOD_EN		0x2
-#define PRCM_FORCE_WAKEUP	0x2
-#define PRCM_FUNCTL		0x0
-
-#define PRCM_EMIF_CLK_ACTIVITY	BIT(2)
-#define PRCM_L3_GCLK_ACTIVITY	BIT(4)
-
-#define PLL_BYPASS_MODE		0x4
-#define ST_MN_BYPASS		0x00000100
-#define ST_DPLL_CLK		0x00000001
-#define CLK_SEL_MASK		0x7ffff
-#define CLK_DIV_MASK		0x1f
-#define CLK_DIV2_MASK		0x7f
-#define CLK_SEL_SHIFT		0x8
-#define CLK_MODE_SEL		0x7
-#define CLK_MODE_MASK		0xfffffff8
-#define CLK_DIV_SEL		0xFFFFFFE0
-#define CPGMAC0_IDLE		0x30000
-#define DPLL_CLKDCOLDO_GATE_CTRL        0x300
-
-const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
-const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
-const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
-const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
-
-static void enable_interface_clocks(void)
-{
-	/* Enable all the Interconnect Modules */
-	writel(PRCM_MOD_EN, &cmper->l3clkctrl);
-	while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN)
-		;
-
-	writel(PRCM_MOD_EN, &cmper->l4lsclkctrl);
-	while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN)
-		;
-
-	writel(PRCM_MOD_EN, &cmper->l4fwclkctrl);
-	while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN)
-		;
-
-	writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl);
-	while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN)
-		;
-
-	writel(PRCM_MOD_EN, &cmper->l3instrclkctrl);
-	while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN)
-		;
-
-	writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
-	while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
-		;
-
-	writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl);
-	while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN)
-		;
-}
-
-/*
- * Force power domain wake up transition
- * Ensure that the corresponding interface clock is active before
- * using the peripheral
- */
-static void power_domain_wkup_transition(void)
-{
-	writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl);
-	writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl);
-	writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl);
-	writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl);
-	writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl);
-}
-
-/*
- * Enable the peripheral clock for required peripherals
- */
-static void enable_per_clocks(void)
-{
-	/* Enable the control module though RBL would have done it*/
-	writel(PRCM_MOD_EN, &cmwkup->wkctrlclkctrl);
-	while (readl(&cmwkup->wkctrlclkctrl) != PRCM_MOD_EN)
-		;
-
-	/* Enable the module clock */
-	writel(PRCM_MOD_EN, &cmper->timer2clkctrl);
-	while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
-		;
-
-	/* Select the Master osc 24 MHZ as Timer2 clock source */
-	writel(0x1, &cmdpll->clktimer2clk);
-
-	/* UART0 */
-	writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
-	while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
-		;
-
-	/* UART1 */
-#ifdef CONFIG_SERIAL2
-	writel(PRCM_MOD_EN, &cmper->uart1clkctrl);
-	while (readl(&cmper->uart1clkctrl) != PRCM_MOD_EN)
-		;
-#endif /* CONFIG_SERIAL2 */
-
-	/* UART2 */
-#ifdef CONFIG_SERIAL3
-	writel(PRCM_MOD_EN, &cmper->uart2clkctrl);
-	while (readl(&cmper->uart2clkctrl) != PRCM_MOD_EN)
-		;
-#endif /* CONFIG_SERIAL3 */
-
-	/* UART3 */
-#ifdef CONFIG_SERIAL4
-	writel(PRCM_MOD_EN, &cmper->uart3clkctrl);
-	while (readl(&cmper->uart3clkctrl) != PRCM_MOD_EN)
-		;
-#endif /* CONFIG_SERIAL4 */
-
-	/* UART4 */
-#ifdef CONFIG_SERIAL5
-	writel(PRCM_MOD_EN, &cmper->uart4clkctrl);
-	while (readl(&cmper->uart4clkctrl) != PRCM_MOD_EN)
-		;
-#endif /* CONFIG_SERIAL5 */
-
-	/* UART5 */
-#ifdef CONFIG_SERIAL6
-	writel(PRCM_MOD_EN, &cmper->uart5clkctrl);
-	while (readl(&cmper->uart5clkctrl) != PRCM_MOD_EN)
-		;
-#endif /* CONFIG_SERIAL6 */
-
-	/* GPMC */
-	writel(PRCM_MOD_EN, &cmper->gpmcclkctrl);
-	while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN)
-		;
-
-	/* ELM */
-	writel(PRCM_MOD_EN, &cmper->elmclkctrl);
-	while (readl(&cmper->elmclkctrl) != PRCM_MOD_EN)
-		;
-
-	/* MMC0*/
-	writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
-	while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
-		;
-
-	/* i2c0 */
-	writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
-	while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)
-		;
-
-	/* gpio1 module */
-	writel(PRCM_MOD_EN, &cmper->gpio1clkctrl);
-	while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN)
-		;
-
-	/* gpio2 module */
-	writel(PRCM_MOD_EN, &cmper->gpio2clkctrl);
-	while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN)
-		;
-
-	/* gpio3 module */
-	writel(PRCM_MOD_EN, &cmper->gpio3clkctrl);
-	while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN)
-		;
-
-	/* i2c1 */
-	writel(PRCM_MOD_EN, &cmper->i2c1clkctrl);
-	while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN)
-		;
-
-	/* Ethernet */
-	writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
-	while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
-		;
-
-	/* spi0 */
-	writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
-	while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
-		;
-
-	/* RTC */
-	writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
-	while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
-		;
-
-	/* MUSB */
-	writel(PRCM_MOD_EN, &cmper->usb0clkctrl);
-	while (readl(&cmper->usb0clkctrl) != PRCM_MOD_EN)
-		;
-}
-
-static void mpu_pll_config(void)
-{
-	u32 clkmode, clksel, div_m2;
-
-	clkmode = readl(&cmwkup->clkmoddpllmpu);
-	clksel = readl(&cmwkup->clkseldpllmpu);
-	div_m2 = readl(&cmwkup->divm2dpllmpu);
-
-	/* Set the PLL to bypass Mode */
-	writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu);
-	while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS)
-		;
-
-	clksel = clksel & (~CLK_SEL_MASK);
-	clksel = clksel | ((MPUPLL_M << CLK_SEL_SHIFT) | MPUPLL_N);
-	writel(clksel, &cmwkup->clkseldpllmpu);
-
-	div_m2 = div_m2 & ~CLK_DIV_MASK;
-	div_m2 = div_m2 | MPUPLL_M2;
-	writel(div_m2, &cmwkup->divm2dpllmpu);
-
-	clkmode = clkmode | CLK_MODE_SEL;
-	writel(clkmode, &cmwkup->clkmoddpllmpu);
-
-	while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK)
-		;
-}
-
-static void core_pll_config(void)
-{
-	u32 clkmode, clksel, div_m4, div_m5, div_m6;
-
-	clkmode = readl(&cmwkup->clkmoddpllcore);
-	clksel = readl(&cmwkup->clkseldpllcore);
-	div_m4 = readl(&cmwkup->divm4dpllcore);
-	div_m5 = readl(&cmwkup->divm5dpllcore);
-	div_m6 = readl(&cmwkup->divm6dpllcore);
-
-	/* Set the PLL to bypass Mode */
-	writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
-
-	while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
-		;
-
-	clksel = clksel & (~CLK_SEL_MASK);
-	clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
-	writel(clksel, &cmwkup->clkseldpllcore);
-
-	div_m4 = div_m4 & ~CLK_DIV_MASK;
-	div_m4 = div_m4 | COREPLL_M4;
-	writel(div_m4, &cmwkup->divm4dpllcore);
-
-	div_m5 = div_m5 & ~CLK_DIV_MASK;
-	div_m5 = div_m5 | COREPLL_M5;
-	writel(div_m5, &cmwkup->divm5dpllcore);
-
-	div_m6 = div_m6 & ~CLK_DIV_MASK;
-	div_m6 = div_m6 | COREPLL_M6;
-	writel(div_m6, &cmwkup->divm6dpllcore);
-
-	clkmode = clkmode | CLK_MODE_SEL;
-	writel(clkmode, &cmwkup->clkmoddpllcore);
-
-	while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
-		;
-}
-
-static void per_pll_config(void)
-{
-	u32 clkmode, clksel, div_m2;
-
-	clkmode = readl(&cmwkup->clkmoddpllper);
-	clksel = readl(&cmwkup->clkseldpllper);
-	div_m2 = readl(&cmwkup->divm2dpllper);
-
-	/* Set the PLL to bypass Mode */
-	writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllper);
-
-	while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS)
-		;
-
-	clksel = clksel & (~CLK_SEL_MASK);
-	clksel = clksel | ((PERPLL_M << CLK_SEL_SHIFT) | PERPLL_N);
-	writel(clksel, &cmwkup->clkseldpllper);
-
-	div_m2 = div_m2 & ~CLK_DIV2_MASK;
-	div_m2 = div_m2 | PERPLL_M2;
-	writel(div_m2, &cmwkup->divm2dpllper);
-
-	clkmode = clkmode | CLK_MODE_SEL;
-	writel(clkmode, &cmwkup->clkmoddpllper);
-
-	while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
-		;
-
-	writel(DPLL_CLKDCOLDO_GATE_CTRL, &cmwkup->clkdcoldodpllper);
-}
-
-void ddr_pll_config(unsigned int ddrpll_m)
-{
-	u32 clkmode, clksel, div_m2;
-
-	clkmode = readl(&cmwkup->clkmoddpllddr);
-	clksel = readl(&cmwkup->clkseldpllddr);
-	div_m2 = readl(&cmwkup->divm2dpllddr);
-
-	/* Set the PLL to bypass Mode */
-	clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE;
-	writel(clkmode, &cmwkup->clkmoddpllddr);
-
-	/* Wait till bypass mode is enabled */
-	while ((readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS)
-				!= ST_MN_BYPASS)
-		;
-
-	clksel = clksel & (~CLK_SEL_MASK);
-	clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N);
-	writel(clksel, &cmwkup->clkseldpllddr);
-
-	div_m2 = div_m2 & CLK_DIV_SEL;
-	div_m2 = div_m2 | DDRPLL_M2;
-	writel(div_m2, &cmwkup->divm2dpllddr);
-
-	clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL;
-	writel(clkmode, &cmwkup->clkmoddpllddr);
-
-	/* Wait till dpll is locked */
-	while ((readl(&cmwkup->idlestdpllddr) & ST_DPLL_CLK) != ST_DPLL_CLK)
-		;
-}
-
-void enable_emif_clocks(void)
-{
-	/* Enable the  EMIF_FW Functional clock */
-	writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
-	/* Enable EMIF0 Clock */
-	writel(PRCM_MOD_EN, &cmper->emifclkctrl);
-	/* Poll if module is functional */
-	while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
-		;
-}
-
-/*
- * Configure the PLL/PRCM for necessary peripherals
- */
-void pll_init()
-{
-	mpu_pll_config();
-	core_pll_config();
-	per_pll_config();
-
-	/* Enable the required interconnect clocks */
-	enable_interface_clocks();
-
-	/* Power domain wake up transition */
-	power_domain_wkup_transition();
-
-	/* Enable the required peripherals */
-	enable_per_clocks();
-}
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h
index 872ff82..786eecf 100644
--- a/arch/arm/include/asm/arch-am33xx/clock.h
+++ b/arch/arm/include/asm/arch-am33xx/clock.h
@@ -19,6 +19,10 @@
 #ifndef _CLOCKS_H_
 #define _CLOCKS_H_
 
+#ifdef CONFIG_AM33XX
 #include <asm/arch/clocks_am33xx.h>
+#elif defined(CONFIG_TI814X)
+#include <asm/arch/clocks_ti814x.h>
+#endif
 
 #endif
diff --git a/arch/arm/include/asm/arch-am33xx/clocks_ti814x.h b/arch/arm/include/asm/arch-am33xx/clocks_ti814x.h
new file mode 100644
index 0000000..4d37470
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/clocks_ti814x.h
@@ -0,0 +1,112 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _CLOCKS_TI814X_H_
+#define _CLOCKS_TI814X_H_
+
+#define DDR_PLL_400		/* Values supported 400,533 */
+
+/* CLK_SRC */
+#define OSC_SRC0		0
+#define OSC_SRC1		1
+
+#define L3_OSC_SRC		OSC_SRC0
+
+#define OSC_0_FREQ		20
+
+#define DCO_HS2_MIN		500
+#define DCO_HS2_MAX		1000
+#define DCO_HS1_MIN		1000
+#define DCO_HS1_MAX		2000
+
+#define SELFREQDCO_HS2		0x00000801
+#define SELFREQDCO_HS1		0x00001001
+
+#define MPU_N			0x1
+#define MPU_M			0x3C
+#define MPU_M2			1
+#define MPU_CLKCTRL		0x1
+
+#define L3_N			19
+#define L3_M			880
+#define L3_M2			4
+#define L3_CLKCTRL		0x801
+
+#define DDR_N			19
+#define DDR_M			666
+#define DDR_M2			2
+#define DDR_CLKCTRL		0x801
+
+/* Clocks are derived from ADPLLJ */
+#define ADPLLJ_CLKCTRL		0x4
+#define ADPLLJ_TENABLE		0x8
+#define ADPLLJ_TENABLEDIV	0xC
+#define ADPLLJ_M2NDIV		0x10
+#define ADPLLJ_MN2DIV		0x14
+#define ADPLLJ_FRACDIV		0x18
+#define ADPLLJ_STATUS		0x24
+
+/* ADPLLJ register values */
+#define ADPLLJ_CLKCTRL_HS2	0x00000801 /* HS2 mode, TINT2 = 1 */
+#define ADPLLJ_CLKCTRL_HS1	0x00001001 /* HS1 mode, TINT2 = 1 */
+#define ADPLLJ_CLKCTRL_CLKDCO	0x201A0000
+
+#define MPU_PLL_BASE			(PLL_SUBSYS_BASE + 0x048)
+#define L3_PLL_BASE			(PLL_SUBSYS_BASE + 0x110)
+#define USB_PLL_BASE			(PLL_SUBSYS_BASE + 0x260)
+#define DDR_PLL_BASE			(PLL_SUBSYS_BASE + 0x290)
+
+#define OSC_SRC_CTRL			(PLL_SUBSYS_BASE + 0x2C0)
+#define OSC_SRC				(PLL_SUBSYS_BASE + 0x2C0)
+#define ARM_CLKSRC			(PLL_SUBSYS_BASE + 0x2C4)
+#define MLB_ATL_CLKSRC			(PLL_SUBSYS_BASE + 0x2CC)
+#define DMTIMER_CLKSRC			(PLL_SUBSYS_BASE + 0x2E0)
+#define CLKOUT_MUX			(PLL_SUBSYS_BASE + 0x2E4)
+#define SYSCLK18_SRC			(PLL_SUBSYS_BASE + 0x2F0)
+#define WDT0_CLKSRC			(PLL_SUBSYS_BASE + 0x2F4)
+
+/* PRCM */
+#define CM_DPLL_OFFSET			(PRCM_BASE + 0x0300)
+
+/*EMIF4 PRCM Defintion*/
+#define CM_DEFAULT_L3_FAST_CLKSTCTRL	(PRCM_BASE + 0x0508)
+#define CM_DEFAULT_EMIF_0_CLKCTRL	(PRCM_BASE + 0x0520)
+#define CM_DEFAULT_EMIF_1_CLKCTRL	(PRCM_BASE + 0x0524)
+#define CM_DEFAULT_DMM_CLKCTRL		(PRCM_BASE + 0x0528)
+#define CM_DEFAULT_FW_CLKCTRL		(PRCM_BASE + 0x052C)
+
+#define CM_ALWON_L3_SLOW_CLKSTCTRL	(PRCM_BASE + 0x1400)
+#define CM_ALWON_UART_0_CLKCTRL		(PRCM_BASE + 0x1550)
+#define CM_ALWON_UART_1_CLKCTRL		(PRCM_BASE + 0x1554)
+#define CM_ALWON_UART_2_CLKCTRL		(PRCM_BASE + 0x1558)
+#define CM_ALWON_GPIO_0_CLKCTRL		(PRCM_BASE + 0x155c)
+#define CM_ALWON_GPIO_0_OPTFCLKEN_DBCLK (PRCM_BASE + 0x155c)
+#define CM_ALWON_WDTIMER_CLKCTRL	(PRCM_BASE + 0x158C)
+#define CM_ALWON_SPI_CLKCTRL		(PRCM_BASE + 0x1590)
+#define CM_ALWON_CONTROL_CLKCTRL	(PRCM_BASE + 0x15C4)
+#define CM_ALWON_HSMMC_CLKCTRL		(PRCM_BASE + 0x1620)
+
+#define CM_DLL_CTRL_NO_OVERRIDE		0
+
+extern void pll_init(void);
+extern void enable_emif_clocks(void);
+extern void enable_dmm_clocks(void);
+
+#endif	/* endif _CLOCKS_TI814X_H_ */
-- 
1.7.9.5

[U-Boot] [PATCH 04/10] am33xx: refactor am33xx mux support and add ti814x support

[Matt Porter]

AM33XX and TI814X have a similar mux though the pinmux register
layout and address space differ. Add a separate ti814x mux include
to support the TI814X-specific differences.

Signed-off-by: Matt Porter <mporter@ti.com>
---
 arch/arm/include/asm/arch-am33xx/mux-am335x.h |  246 ++++++++++++++++++++
 arch/arm/include/asm/arch-am33xx/mux-ti814x.h |  310 +++++++++++++++++++++++++
 arch/arm/include/asm/arch-am33xx/mux.h        |  230 +-----------------
 3 files changed, 562 insertions(+), 224 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-am33xx/mux-am335x.h
 create mode 100644 arch/arm/include/asm/arch-am33xx/mux-ti814x.h

diff --git a/arch/arm/include/asm/arch-am33xx/mux-am335x.h b/arch/arm/include/asm/arch-am33xx/mux-am335x.h
new file mode 100644
index 0000000..7258135
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/mux-am335x.h
@@ -0,0 +1,246 @@
+/*
+ * mux.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MUX_AM335X_H_
+#define _MUX_AM335X_H_
+
+#include <common.h>
+#include <asm/io.h>
+
+#define MUX_CFG(value, offset)	\
+	__raw_writel(value, (CTRL_BASE + offset));
+
+/* PAD Control Fields */
+#define SLEWCTRL	(0x1 << 6)
+#define RXACTIVE	(0x1 << 5)
+#define PULLUP_EN	(0x1 << 4) /* Pull UP Selection */
+#define PULLUDEN	(0x0 << 3) /* Pull up enabled */
+#define PULLUDDIS	(0x1 << 3) /* Pull up disabled */
+#define MODE(val)	val	/* used for Readability */
+
+/*
+ * PAD CONTROL OFFSETS
+ * Field names corresponds to the pad signal name
+ */
+struct pad_signals {
+	int gpmc_ad0;
+	int gpmc_ad1;
+	int gpmc_ad2;
+	int gpmc_ad3;
+	int gpmc_ad4;
+	int gpmc_ad5;
+	int gpmc_ad6;
+	int gpmc_ad7;
+	int gpmc_ad8;
+	int gpmc_ad9;
+	int gpmc_ad10;
+	int gpmc_ad11;
+	int gpmc_ad12;
+	int gpmc_ad13;
+	int gpmc_ad14;
+	int gpmc_ad15;
+	int gpmc_a0;
+	int gpmc_a1;
+	int gpmc_a2;
+	int gpmc_a3;
+	int gpmc_a4;
+	int gpmc_a5;
+	int gpmc_a6;
+	int gpmc_a7;
+	int gpmc_a8;
+	int gpmc_a9;
+	int gpmc_a10;
+	int gpmc_a11;
+	int gpmc_wait0;
+	int gpmc_wpn;
+	int gpmc_be1n;
+	int gpmc_csn0;
+	int gpmc_csn1;
+	int gpmc_csn2;
+	int gpmc_csn3;
+	int gpmc_clk;
+	int gpmc_advn_ale;
+	int gpmc_oen_ren;
+	int gpmc_wen;
+	int gpmc_be0n_cle;
+	int lcd_data0;
+	int lcd_data1;
+	int lcd_data2;
+	int lcd_data3;
+	int lcd_data4;
+	int lcd_data5;
+	int lcd_data6;
+	int lcd_data7;
+	int lcd_data8;
+	int lcd_data9;
+	int lcd_data10;
+	int lcd_data11;
+	int lcd_data12;
+	int lcd_data13;
+	int lcd_data14;
+	int lcd_data15;
+	int lcd_vsync;
+	int lcd_hsync;
+	int lcd_pclk;
+	int lcd_ac_bias_en;
+	int mmc0_dat3;
+	int mmc0_dat2;
+	int mmc0_dat1;
+	int mmc0_dat0;
+	int mmc0_clk;
+	int mmc0_cmd;
+	int mii1_col;
+	int mii1_crs;
+	int mii1_rxerr;
+	int mii1_txen;
+	int mii1_rxdv;
+	int mii1_txd3;
+	int mii1_txd2;
+	int mii1_txd1;
+	int mii1_txd0;
+	int mii1_txclk;
+	int mii1_rxclk;
+	int mii1_rxd3;
+	int mii1_rxd2;
+	int mii1_rxd1;
+	int mii1_rxd0;
+	int rmii1_refclk;
+	int mdio_data;
+	int mdio_clk;
+	int spi0_sclk;
+	int spi0_d0;
+	int spi0_d1;
+	int spi0_cs0;
+	int spi0_cs1;
+	int ecap0_in_pwm0_out;
+	int uart0_ctsn;
+	int uart0_rtsn;
+	int uart0_rxd;
+	int uart0_txd;
+	int uart1_ctsn;
+	int uart1_rtsn;
+	int uart1_rxd;
+	int uart1_txd;
+	int i2c0_sda;
+	int i2c0_scl;
+	int mcasp0_aclkx;
+	int mcasp0_fsx;
+	int mcasp0_axr0;
+	int mcasp0_ahclkr;
+	int mcasp0_aclkr;
+	int mcasp0_fsr;
+	int mcasp0_axr1;
+	int mcasp0_ahclkx;
+	int xdma_event_intr0;
+	int xdma_event_intr1;
+	int nresetin_out;
+	int porz;
+	int nnmi;
+	int osc0_in;
+	int osc0_out;
+	int rsvd1;
+	int tms;
+	int tdi;
+	int tdo;
+	int tck;
+	int ntrst;
+	int emu0;
+	int emu1;
+	int osc1_in;
+	int osc1_out;
+	int pmic_power_en;
+	int rtc_porz;
+	int rsvd2;
+	int ext_wakeup;
+	int enz_kaldo_1p8v;
+	int usb0_dm;
+	int usb0_dp;
+	int usb0_ce;
+	int usb0_id;
+	int usb0_vbus;
+	int usb0_drvvbus;
+	int usb1_dm;
+	int usb1_dp;
+	int usb1_ce;
+	int usb1_id;
+	int usb1_vbus;
+	int usb1_drvvbus;
+	int ddr_resetn;
+	int ddr_csn0;
+	int ddr_cke;
+	int ddr_ck;
+	int ddr_nck;
+	int ddr_casn;
+	int ddr_rasn;
+	int ddr_wen;
+	int ddr_ba0;
+	int ddr_ba1;
+	int ddr_ba2;
+	int ddr_a0;
+	int ddr_a1;
+	int ddr_a2;
+	int ddr_a3;
+	int ddr_a4;
+	int ddr_a5;
+	int ddr_a6;
+	int ddr_a7;
+	int ddr_a8;
+	int ddr_a9;
+	int ddr_a10;
+	int ddr_a11;
+	int ddr_a12;
+	int ddr_a13;
+	int ddr_a14;
+	int ddr_a15;
+	int ddr_odt;
+	int ddr_d0;
+	int ddr_d1;
+	int ddr_d2;
+	int ddr_d3;
+	int ddr_d4;
+	int ddr_d5;
+	int ddr_d6;
+	int ddr_d7;
+	int ddr_d8;
+	int ddr_d9;
+	int ddr_d10;
+	int ddr_d11;
+	int ddr_d12;
+	int ddr_d13;
+	int ddr_d14;
+	int ddr_d15;
+	int ddr_dqm0;
+	int ddr_dqm1;
+	int ddr_dqs0;
+	int ddr_dqsn0;
+	int ddr_dqs1;
+	int ddr_dqsn1;
+	int ddr_vref;
+	int ddr_vtp;
+	int ddr_strben0;
+	int ddr_strben1;
+	int ain7;
+	int ain6;
+	int ain5;
+	int ain4;
+	int ain3;
+	int ain2;
+	int ain1;
+	int ain0;
+	int vrefp;
+	int vrefn;
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-am33xx/mux-ti814x.h b/arch/arm/include/asm/arch-am33xx/mux-ti814x.h
new file mode 100644
index 0000000..df66354
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/mux-ti814x.h
@@ -0,0 +1,310 @@
+/*
+ * mux-ti814x.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MUX_TI814X_H_
+#define _MUX_TI814X_H_
+
+/* PAD Control Fields */
+#define PINCNTL_RSV_MSK	(0x3 << 18) /* Reserved bitmask */
+#define PULLUP_EN	(0x1 << 17) /* Pull UP Selection */
+#define PULLUDEN	(0x0 << 16) /* Pull up enabled */
+#define PULLUDDIS	(0x1 << 16) /* Pull up disabled */
+#define MODE(val)	val	/* used for Readability */
+
+#define MUX_CFG(value, offset)				\
+{							\
+	int tmp;					\
+	tmp = __raw_readl(CTRL_BASE + offset);		\
+	tmp &= PINCNTL_RSV_MSK;				\
+	__raw_writel(tmp | value, (CTRL_BASE + offset));\
+}
+
+/*
+ * PAD CONTROL OFFSETS
+ * Field names corresponds to the pad signal name
+ */
+struct pad_signals {
+	int pincntl1;
+	int pincntl2;
+	int pincntl3;
+	int pincntl4;
+	int pincntl5;
+	int pincntl6;
+	int pincntl7;
+	int pincntl8;
+	int pincntl9;
+	int pincntl10;
+	int pincntl11;
+	int pincntl12;
+	int pincntl13;
+	int pincntl14;
+	int pincntl15;
+	int pincntl16;
+	int pincntl17;
+	int pincntl18;
+	int pincntl19;
+	int pincntl20;
+	int pincntl21;
+	int pincntl22;
+	int pincntl23;
+	int pincntl24;
+	int pincntl25;
+	int pincntl26;
+	int pincntl27;
+	int pincntl28;
+	int pincntl29;
+	int pincntl30;
+	int pincntl31;
+	int pincntl32;
+	int pincntl33;
+	int pincntl34;
+	int pincntl35;
+	int pincntl36;
+	int pincntl37;
+	int pincntl38;
+	int pincntl39;
+	int pincntl40;
+	int pincntl41;
+	int pincntl42;
+	int pincntl43;
+	int pincntl44;
+	int pincntl45;
+	int pincntl46;
+	int pincntl47;
+	int pincntl48;
+	int pincntl49;
+	int pincntl50;
+	int pincntl51;
+	int pincntl52;
+	int pincntl53;
+	int pincntl54;
+	int pincntl55;
+	int pincntl56;
+	int pincntl57;
+	int pincntl58;
+	int pincntl59;
+	int pincntl60;
+	int pincntl61;
+	int pincntl62;
+	int pincntl63;
+	int pincntl64;
+	int pincntl65;
+	int pincntl66;
+	int pincntl67;
+	int pincntl68;
+	int pincntl69;
+	int pincntl70;
+	int pincntl71;
+	int pincntl72;
+	int pincntl73;
+	int pincntl74;
+	int pincntl75;
+	int pincntl76;
+	int pincntl77;
+	int pincntl78;
+	int pincntl79;
+	int pincntl80;
+	int pincntl81;
+	int pincntl82;
+	int pincntl83;
+	int pincntl84;
+	int pincntl85;
+	int pincntl86;
+	int pincntl87;
+	int pincntl88;
+	int pincntl89;
+	int pincntl90;
+	int pincntl91;
+	int pincntl92;
+	int pincntl93;
+	int pincntl94;
+	int pincntl95;
+	int pincntl96;
+	int pincntl97;
+	int pincntl98;
+	int pincntl99;
+	int pincntl100;
+	int pincntl101;
+	int pincntl102;
+	int pincntl103;
+	int pincntl104;
+	int pincntl105;
+	int pincntl106;
+	int pincntl107;
+	int pincntl108;
+	int pincntl109;
+	int pincntl110;
+	int pincntl111;
+	int pincntl112;
+	int pincntl113;
+	int pincntl114;
+	int pincntl115;
+	int pincntl116;
+	int pincntl117;
+	int pincntl118;
+	int pincntl119;
+	int pincntl120;
+	int pincntl121;
+	int pincntl122;
+	int pincntl123;
+	int pincntl124;
+	int pincntl125;
+	int pincntl126;
+	int pincntl127;
+	int pincntl128;
+	int pincntl129;
+	int pincntl130;
+	int pincntl131;
+	int pincntl132;
+	int pincntl133;
+	int pincntl134;
+	int pincntl135;
+	int pincntl136;
+	int pincntl137;
+	int pincntl138;
+	int pincntl139;
+	int pincntl140;
+	int pincntl141;
+	int pincntl142;
+	int pincntl143;
+	int pincntl144;
+	int pincntl145;
+	int pincntl146;
+	int pincntl147;
+	int pincntl148;
+	int pincntl149;
+	int pincntl150;
+	int pincntl151;
+	int pincntl152;
+	int pincntl153;
+	int pincntl154;
+	int pincntl155;
+	int pincntl156;
+	int pincntl157;
+	int pincntl158;
+	int pincntl159;
+	int pincntl160;
+	int pincntl161;
+	int pincntl162;
+	int pincntl163;
+	int pincntl164;
+	int pincntl165;
+	int pincntl166;
+	int pincntl167;
+	int pincntl168;
+	int pincntl169;
+	int pincntl170;
+	int pincntl171;
+	int pincntl172;
+	int pincntl173;
+	int pincntl174;
+	int pincntl175;
+	int pincntl176;
+	int pincntl177;
+	int pincntl178;
+	int pincntl179;
+	int pincntl180;
+	int pincntl181;
+	int pincntl182;
+	int pincntl183;
+	int pincntl184;
+	int pincntl185;
+	int pincntl186;
+	int pincntl187;
+	int pincntl188;
+	int pincntl189;
+	int pincntl190;
+	int pincntl191;
+	int pincntl192;
+	int pincntl193;
+	int pincntl194;
+	int pincntl195;
+	int pincntl196;
+	int pincntl197;
+	int pincntl198;
+	int pincntl199;
+	int pincntl200;
+	int pincntl201;
+	int pincntl202;
+	int pincntl203;
+	int pincntl204;
+	int pincntl205;
+	int pincntl206;
+	int pincntl207;
+	int pincntl208;
+	int pincntl209;
+	int pincntl210;
+	int pincntl211;
+	int pincntl212;
+	int pincntl213;
+	int pincntl214;
+	int pincntl215;
+	int pincntl216;
+	int pincntl217;
+	int pincntl218;
+	int pincntl219;
+	int pincntl220;
+	int pincntl221;
+	int pincntl222;
+	int pincntl223;
+	int pincntl224;
+	int pincntl225;
+	int pincntl226;
+	int pincntl227;
+	int pincntl228;
+	int pincntl229;
+	int pincntl230;
+	int pincntl231;
+	int pincntl232;
+	int pincntl233;
+	int pincntl234;
+	int pincntl235;
+	int pincntl236;
+	int pincntl237;
+	int pincntl238;
+	int pincntl239;
+	int pincntl240;
+	int pincntl241;
+	int pincntl242;
+	int pincntl243;
+	int pincntl244;
+	int pincntl245;
+	int pincntl246;
+	int pincntl247;
+	int pincntl248;
+	int pincntl249;
+	int pincntl250;
+	int pincntl251;
+	int pincntl252;
+	int pincntl253;
+	int pincntl254;
+	int pincntl255;
+	int pincntl256;
+	int pincntl257;
+	int pincntl258;
+	int pincntl259;
+	int pincntl260;
+	int pincntl261;
+	int pincntl262;
+	int pincntl263;
+	int pincntl264;
+	int pincntl265;
+	int pincntl266;
+	int pincntl267;
+	int pincntl268;
+	int pincntl269;
+	int pincntl270;
+};
+#endif
diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h
index aed6b00..47d88b9 100644
--- a/arch/arm/include/asm/arch-am33xx/mux.h
+++ b/arch/arm/include/asm/arch-am33xx/mux.h
@@ -19,233 +19,15 @@
 #include <common.h>
 #include <asm/io.h>
 
-#define MUX_CFG(value, offset)	\
-	__raw_writel(value, (CTRL_BASE + offset));
-
-/* PAD Control Fields */
-#define SLEWCTRL	(0x1 << 6)
-#define RXACTIVE	(0x1 << 5)
-#define PULLUP_EN	(0x1 << 4) /* Pull UP Selection */
-#define PULLUDEN	(0x0 << 3) /* Pull up enabled */
-#define PULLUDDIS	(0x1 << 3) /* Pull up disabled */
-#define MODE(val)	val	/* used for Readability */
-
-/*
- * PAD CONTROL OFFSETS
- * Field names corresponds to the pad signal name
- */
-struct pad_signals {
-	int gpmc_ad0;
-	int gpmc_ad1;
-	int gpmc_ad2;
-	int gpmc_ad3;
-	int gpmc_ad4;
-	int gpmc_ad5;
-	int gpmc_ad6;
-	int gpmc_ad7;
-	int gpmc_ad8;
-	int gpmc_ad9;
-	int gpmc_ad10;
-	int gpmc_ad11;
-	int gpmc_ad12;
-	int gpmc_ad13;
-	int gpmc_ad14;
-	int gpmc_ad15;
-	int gpmc_a0;
-	int gpmc_a1;
-	int gpmc_a2;
-	int gpmc_a3;
-	int gpmc_a4;
-	int gpmc_a5;
-	int gpmc_a6;
-	int gpmc_a7;
-	int gpmc_a8;
-	int gpmc_a9;
-	int gpmc_a10;
-	int gpmc_a11;
-	int gpmc_wait0;
-	int gpmc_wpn;
-	int gpmc_be1n;
-	int gpmc_csn0;
-	int gpmc_csn1;
-	int gpmc_csn2;
-	int gpmc_csn3;
-	int gpmc_clk;
-	int gpmc_advn_ale;
-	int gpmc_oen_ren;
-	int gpmc_wen;
-	int gpmc_be0n_cle;
-	int lcd_data0;
-	int lcd_data1;
-	int lcd_data2;
-	int lcd_data3;
-	int lcd_data4;
-	int lcd_data5;
-	int lcd_data6;
-	int lcd_data7;
-	int lcd_data8;
-	int lcd_data9;
-	int lcd_data10;
-	int lcd_data11;
-	int lcd_data12;
-	int lcd_data13;
-	int lcd_data14;
-	int lcd_data15;
-	int lcd_vsync;
-	int lcd_hsync;
-	int lcd_pclk;
-	int lcd_ac_bias_en;
-	int mmc0_dat3;
-	int mmc0_dat2;
-	int mmc0_dat1;
-	int mmc0_dat0;
-	int mmc0_clk;
-	int mmc0_cmd;
-	int mii1_col;
-	int mii1_crs;
-	int mii1_rxerr;
-	int mii1_txen;
-	int mii1_rxdv;
-	int mii1_txd3;
-	int mii1_txd2;
-	int mii1_txd1;
-	int mii1_txd0;
-	int mii1_txclk;
-	int mii1_rxclk;
-	int mii1_rxd3;
-	int mii1_rxd2;
-	int mii1_rxd1;
-	int mii1_rxd0;
-	int rmii1_refclk;
-	int mdio_data;
-	int mdio_clk;
-	int spi0_sclk;
-	int spi0_d0;
-	int spi0_d1;
-	int spi0_cs0;
-	int spi0_cs1;
-	int ecap0_in_pwm0_out;
-	int uart0_ctsn;
-	int uart0_rtsn;
-	int uart0_rxd;
-	int uart0_txd;
-	int uart1_ctsn;
-	int uart1_rtsn;
-	int uart1_rxd;
-	int uart1_txd;
-	int i2c0_sda;
-	int i2c0_scl;
-	int mcasp0_aclkx;
-	int mcasp0_fsx;
-	int mcasp0_axr0;
-	int mcasp0_ahclkr;
-	int mcasp0_aclkr;
-	int mcasp0_fsr;
-	int mcasp0_axr1;
-	int mcasp0_ahclkx;
-	int xdma_event_intr0;
-	int xdma_event_intr1;
-	int nresetin_out;
-	int porz;
-	int nnmi;
-	int osc0_in;
-	int osc0_out;
-	int rsvd1;
-	int tms;
-	int tdi;
-	int tdo;
-	int tck;
-	int ntrst;
-	int emu0;
-	int emu1;
-	int osc1_in;
-	int osc1_out;
-	int pmic_power_en;
-	int rtc_porz;
-	int rsvd2;
-	int ext_wakeup;
-	int enz_kaldo_1p8v;
-	int usb0_dm;
-	int usb0_dp;
-	int usb0_ce;
-	int usb0_id;
-	int usb0_vbus;
-	int usb0_drvvbus;
-	int usb1_dm;
-	int usb1_dp;
-	int usb1_ce;
-	int usb1_id;
-	int usb1_vbus;
-	int usb1_drvvbus;
-	int ddr_resetn;
-	int ddr_csn0;
-	int ddr_cke;
-	int ddr_ck;
-	int ddr_nck;
-	int ddr_casn;
-	int ddr_rasn;
-	int ddr_wen;
-	int ddr_ba0;
-	int ddr_ba1;
-	int ddr_ba2;
-	int ddr_a0;
-	int ddr_a1;
-	int ddr_a2;
-	int ddr_a3;
-	int ddr_a4;
-	int ddr_a5;
-	int ddr_a6;
-	int ddr_a7;
-	int ddr_a8;
-	int ddr_a9;
-	int ddr_a10;
-	int ddr_a11;
-	int ddr_a12;
-	int ddr_a13;
-	int ddr_a14;
-	int ddr_a15;
-	int ddr_odt;
-	int ddr_d0;
-	int ddr_d1;
-	int ddr_d2;
-	int ddr_d3;
-	int ddr_d4;
-	int ddr_d5;
-	int ddr_d6;
-	int ddr_d7;
-	int ddr_d8;
-	int ddr_d9;
-	int ddr_d10;
-	int ddr_d11;
-	int ddr_d12;
-	int ddr_d13;
-	int ddr_d14;
-	int ddr_d15;
-	int ddr_dqm0;
-	int ddr_dqm1;
-	int ddr_dqs0;
-	int ddr_dqsn0;
-	int ddr_dqs1;
-	int ddr_dqsn1;
-	int ddr_vref;
-	int ddr_vtp;
-	int ddr_strben0;
-	int ddr_strben1;
-	int ain7;
-	int ain6;
-	int ain5;
-	int ain4;
-	int ain3;
-	int ain2;
-	int ain1;
-	int ain0;
-	int vrefp;
-	int vrefn;
-};
+#ifdef CONFIG_AM33XX
+#include <asm/arch/mux-am335x.h>
+#elif defined(CONFIG_TI814X)
+#include <asm/arch/mux-ti814x.h>
+#endif
 
 struct module_pin_mux {
 	short reg_offset;
-	unsigned char val;
+	unsigned int val;
 };
 
 /* Pad control register offset */
-- 
1.7.9.5

[U-Boot] [PATCH 05/10] am33xx: add ti814x specific register definitions

[Matt Porter]

Support the ti814x specific register definitions within
arch-am33xx.

Signed-off-by: Matt Porter <mporter@ti.com>
---
 arch/arm/cpu/armv7/am33xx/sys_info.c        |    3 +++
 arch/arm/include/asm/arch-am33xx/cpu.h      |   11 +++++----
 arch/arm/include/asm/arch-am33xx/hardware.h |   32 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-am33xx/omap.h     |    7 ++++++
 arch/arm/include/asm/arch-am33xx/spl.h      |    5 +++++
 5 files changed, 54 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c
index 507b618..402127c 100644
--- a/arch/arm/cpu/armv7/am33xx/sys_info.c
+++ b/arch/arm/cpu/armv7/am33xx/sys_info.c
@@ -98,6 +98,9 @@ int print_cpuinfo(void)
 	case AM335X:
 		cpu_s = "AM335X";
 		break;
+	case TI81XX:
+		cpu_s = "TI81XX";
+		break;
 	default:
 		cpu_s = "Unknown cpu type";
 		break;
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 16e8a80..3d3a7c8 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -42,9 +42,10 @@
 #define HS_DEVICE			0x2
 #define GP_DEVICE			0x3
 
-/* cpu-id for AM33XX family */
+/* cpu-id for AM33XX and TI81XX family */
 #define AM335X				0xB944
-#define DEVICE_ID			0x44E10600
+#define TI81XX				0xB81E
+#define DEVICE_ID			(CTRL_BASE + 0x0600)
 
 /* This gives the status of the boot mode pins on the evm */
 #define SYSBOOT_MASK			(BIT(0) | BIT(1) | BIT(2)\
@@ -52,9 +53,11 @@
 
 /* Reset control */
 #ifdef CONFIG_AM33XX
-#define PRM_RSTCTRL			0x44E00F00
-#define PRM_RSTST			0x44E00F08
+#define PRM_RSTCTRL			(PRCM_BASE + 0x0F00)
+#elif defined(CONFIG_TI814X)
+#define PRM_RSTCTRL			(PRCM_BASE + 0x00A0)
 #endif
+#define PRM_RSTST			(PRM_RSTCTRL + 8)
 #define PRM_RSTCTRL_RESET		0x01
 #define PRM_RSTST_WARM_RESET_MASK	0x232
 
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
index 41ab2c0..786c159 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -20,9 +20,14 @@
 #define __AM33XX_HARDWARE_H
 
 #include <asm/arch/omap.h>
+#include <config.h>
 
 /* Module base addresses */
+#ifdef CONFIG_AM33XX
 #define UART0_BASE			0x44E09000
+#elif defined(CONFIG_TI814X)
+#define UART0_BASE			0x48020000
+#endif
 
 /* DM Timer base addresses */
 #define DM_TIMER0_BASE			0x4802C000
@@ -37,20 +42,39 @@
 /* GPIO Base address */
 #define GPIO0_BASE			0x48032000
 #define GPIO1_BASE			0x4804C000
+#ifdef CONFIG_AM33XX
 #define GPIO2_BASE			0x481AC000
+#endif
 
 /* BCH Error Location Module */
 #define ELM_BASE			0x48080000
 
 /* Watchdog Timer */
+#ifdef CONFIG_AM33XX
 #define WDT_BASE			0x44E35000
+#elif defined(CONFIG_TI814X)
+#define WDT_BASE			0x481C7000
+#endif
 
 /* Control Module Base Address */
+#ifdef CONFIG_AM33XX
 #define CTRL_BASE			0x44E10000
 #define CTRL_DEVICE_BASE		0x44E10600
+#elif defined(CONFIG_TI814X)
+#define CTRL_BASE			0x48140000
+#endif
 
 /* PRCM Base Address */
+#ifdef CONFIG_AM33XX
 #define PRCM_BASE			0x44E00000
+#elif defined(CONFIG_TI814X)
+#define PRCM_BASE			0x48180000
+#endif
+
+/* PLL Subsystem Base Address */
+#ifdef CONFIG_TI814X
+#define PLL_SUBSYS_BASE			0x481C5000
+#endif
 
 /* EMIF Base address */
 #define EMIF4_0_CFG_BASE		0x4C000000
@@ -99,10 +123,18 @@
 
 /* CPSW Config space */
 #define CPSW_BASE			0x4A100000
+#ifdef CONFIG_AM33XX
 #define CPSW_MDIO_BASE			0x4A101000
+#elif defined(CONFIG_TI814X)
+#define CPSW_MDIO_BASE			0x4A100800
+#endif
 
 /* RTC base address */
+#ifdef CONFIG_AM33XX
 #define RTC_BASE			0x44E3E000
+#elif defined(CONFIG_TI814X)
+#define RTC_BASE			0x480C0000
+#endif
 
 /* OTG */
 #define USB0_OTG_BASE			0x47401000
diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h
index 850f8a5..ba4f6d2 100644
--- a/arch/arm/include/asm/arch-am33xx/omap.h
+++ b/arch/arm/include/asm/arch-am33xx/omap.h
@@ -23,13 +23,20 @@
 #ifndef _OMAP_H_
 #define _OMAP_H_
 
+#include <config.h>
+
 /*
  * Non-secure SRAM Addresses
  * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
  * at 0x40304000(EMU base) so that our code works for both EMU and GP
  */
+#ifdef CONFIG_AM33XX
 #define NON_SECURE_SRAM_START	0x40304000
 #define NON_SECURE_SRAM_END	0x4030E000
+#elif defined(CONFIG_TI814X)
+#define NON_SECURE_SRAM_START	0x40300000
+#define NON_SECURE_SRAM_END	0x40320000
+#endif
 
 /* ROM code defines */
 /* Boot device */
diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h
index 644ff35..9b5fe9e 100644
--- a/arch/arm/include/asm/arch-am33xx/spl.h
+++ b/arch/arm/include/asm/arch-am33xx/spl.h
@@ -25,8 +25,13 @@
 
 #define BOOT_DEVICE_XIP       	2
 #define BOOT_DEVICE_NAND	5
+#ifdef CONFIG_AM33XX
 #define BOOT_DEVICE_MMC1	8
 #define BOOT_DEVICE_MMC2	9	/* eMMC or daughter card */
+#elif defined(CONFIG_TI814X)
+#define BOOT_DEVICE_MMC1	9
+#define BOOT_DEVICE_MMC2	8	/* ROM only supports 2nd instance */
+#endif
 #define BOOT_DEVICE_SPI		11
 #define BOOT_DEVICE_UART	65
 #define BOOT_DEVICE_CPGMAC	70
-- 
1.7.9.5

[U-Boot] [PATCH 06/10] am33xx: add dmm support to emif4 library

[Matt Porter]

Adds a config_dmm() routine to support TI814X DMM configuration.

Signed-off-by: Matt Porter <mporter@ti.com>
---
 arch/arm/cpu/armv7/am33xx/emif4.c           |   17 +++++++++++++++++
 arch/arm/include/asm/arch-am33xx/ddr_defs.h |    5 +++++
 2 files changed, 22 insertions(+)

diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index 0c617fa..27547be 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -44,11 +44,28 @@ void dram_init_banksize(void)
 
 
 #ifdef CONFIG_SPL_BUILD
+static struct dmm_lisa_map_regs *hw_lisa_map_regs =
+				(struct dmm_lisa_map_regs *)DMM_BASE;
 static struct vtp_reg *vtpreg[2] = {
 				(struct vtp_reg *)VTP0_CTRL_ADDR,
 				(struct vtp_reg *)VTP1_CTRL_ADDR};
 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
 
+void config_dmm(const struct dmm_lisa_map_regs *regs)
+{
+	enable_dmm_clocks();
+
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
+	writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
+
+	writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
+	writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
+	writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
+	writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
+}
+
 static void config_vtp(int nr)
 {
 	writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 8bf25a0..943b4ce 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -66,6 +66,11 @@
 #define MT41J128MJT125_IOCTRL_VALUE		0x18B
 
 /**
+ * Configure DMM
+ */
+void config_dmm(const struct dmm_lisa_map_regs *regs);
+
+/**
  * Configure SDRAM
  */
 void config_sdram(const struct emif_regs *regs, int nr);
-- 
1.7.9.5

[U-Boot] [PATCH 07/10] ti814x_evm: add ti814x evm board support

[Matt Porter]

Add TI814X EVM board directory and config file.

Signed-off-by: Matt Porter <mporter@ti.com>
---
 board/ti/ti814x/Makefile     |   46 +++++++++
 board/ti/ti814x/evm.c        |  198 +++++++++++++++++++++++++++++++++++++++
 board/ti/ti814x/evm.h        |    7 ++
 board/ti/ti814x/mux.c        |   51 ++++++++++
 include/configs/ti814x_evm.h |  213 ++++++++++++++++++++++++++++++++++++++++++
 5 files changed, 515 insertions(+)
 create mode 100644 board/ti/ti814x/Makefile
 create mode 100644 board/ti/ti814x/evm.c
 create mode 100644 board/ti/ti814x/evm.h
 create mode 100644 board/ti/ti814x/mux.c
 create mode 100644 include/configs/ti814x_evm.h

diff --git a/board/ti/ti814x/Makefile b/board/ti/ti814x/Makefile
new file mode 100644
index 0000000..09d2422
--- /dev/null
+++ b/board/ti/ti814x/Makefile
@@ -0,0 +1,46 @@
+#
+# Makefile
+#
+# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed "as is" WITHOUT ANY WARRANTY of any
+# kind, whether express or implied; without even the implied warranty
+# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+ifdef CONFIG_SPL_BUILD
+COBJS	:= mux.o
+endif
+
+COBJS	+= evm.o
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
new file mode 100644
index 0000000..53912d1
--- /dev/null
+++ b/board/ti/ti814x/evm.c
@@ -0,0 +1,198 @@
+/*
+ * evm.c
+ *
+ * Board functions for TI814x EVM
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include "evm.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
+#ifdef CONFIG_SPL_BUILD
+static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+#endif
+
+/* UART Defines */
+#ifdef CONFIG_SPL_BUILD
+#define UART_RESET		(0x1 << 1)
+#define UART_CLK_RUNNING_MASK	0x1
+#define UART_SMART_IDLE_EN	(0x1 << 0x3)
+
+static void rtc32k_enable(void)
+{
+	struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
+
+	/*
+	 * Unlock the RTC's registers.  For more details please see the
+	 * RTC_SS section of the TRM.  In order to unlock we need to
+	 * write these specific values (keys) in this order.
+	 */
+	writel(0x83e70b13, &rtc->kick0r);
+	writel(0x95a4f1e0, &rtc->kick1r);
+
+	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
+	writel((1 << 3) | (1 << 6), &rtc->osc);
+}
+
+static void uart_enable(void)
+{
+	u32 regVal;
+
+	/* UART softreset */
+	regVal = readl(&uart_base->uartsyscfg);
+	regVal |= UART_RESET;
+	writel(regVal, &uart_base->uartsyscfg);
+	while ((readl(&uart_base->uartsyssts) &
+		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
+		;
+
+	/* Disable smart idle */
+	regVal = readl(&uart_base->uartsyscfg);
+	regVal |= UART_SMART_IDLE_EN;
+	writel(regVal, &uart_base->uartsyscfg);
+}
+
+static void wdt_disable(void)
+{
+	writel(0xAAAA, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+	writel(0x5555, &wdtimer->wdtwspr);
+	while (readl(&wdtimer->wdtwwps) != 0x0)
+		;
+}
+
+static const struct cmd_control evm_ddr2_cctrl_data = {
+	.cmd0csratio	= 0x80,
+	.cmd0dldiff	= 0x04,
+	.cmd0iclkout	= 0x00,
+
+	.cmd1csratio	= 0x80,
+	.cmd1dldiff	= 0x04,
+	.cmd1iclkout	= 0x00,
+
+	.cmd2csratio	= 0x80,
+	.cmd2dldiff	= 0x04,
+	.cmd2iclkout	= 0x00,
+};
+
+static const struct emif_regs evm_ddr2_emif0_regs = {
+	.sdram_config			= 0x40801ab2,
+	.ref_ctrl			= 0x10000c30,
+	.sdram_tim1			= 0x0aaaf552,
+	.sdram_tim2			= 0x043631d2,
+	.sdram_tim3			= 0x00000327,
+	.emif_ddr_phy_ctlr_1		= 0x00000007
+};
+
+static const struct emif_regs evm_ddr2_emif1_regs = {
+	.sdram_config			= 0x40801ab2,
+	.ref_ctrl			= 0x10000c30,
+	.sdram_tim1			= 0x0aaaf552,
+	.sdram_tim2			= 0x043631d2,
+	.sdram_tim3			= 0x00000327,
+	.emif_ddr_phy_ctlr_1		= 0x00000007
+};
+
+const struct dmm_lisa_map_regs evm_lisa_map_regs = {
+	.dmm_lisa_map_0			= 0x00000000,
+	.dmm_lisa_map_1			= 0x00000000,
+	.dmm_lisa_map_2			= 0x806c0300,
+	.dmm_lisa_map_3			= 0x806c0300,
+};
+
+static const struct ddr_data evm_ddr2_data = {
+	.datardsratio0		= ((0x35<<10) | (0x35<<0)),
+	.datawdsratio0		= ((0x20<<10) | (0x20<<0)),
+	.datawiratio0		= ((0<<10) | (0<<0)),
+	.datagiratio0		= ((0<<10) | (0<<0)),
+	.datafwsratio0		= ((0x90<<10) | (0x90<<0)),
+	.datawrsratio0		= ((0x50<<10) | (0x50<<0)),
+	.datauserank0delay	= 1,
+	.datadldiff0		= 0x4,
+};
+#endif
+
+/*
+ * early system init of muxing and clocks.
+ */
+void s_init(void)
+{
+#ifdef CONFIG_SPL_BUILD
+	/* WDT1 is already running when the bootloader gets control
+	 * Disable it to avoid "random" resets
+	 */
+	wdt_disable();
+
+	/* Setup the PLLs and the clocks for the peripherals */
+	pll_init();
+
+	/* Enable RTC32K clock */
+	rtc32k_enable();
+
+	/* Set UART pins */
+	enable_uart0_pin_mux();
+
+	/* Set MMC pins */
+	enable_mmc1_pin_mux();
+
+	/* Enable UART */
+	uart_enable();
+
+	gd = &gdata;
+
+	preloader_console_init();
+
+	config_dmm(&evm_lisa_map_regs);
+
+	config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
+		   &evm_ddr2_emif0_regs, 0);
+	config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
+		   &evm_ddr2_emif1_regs, 1);
+#endif
+}
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+	gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
+	return 0;
+}
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
+int board_mmc_init(bd_t *bis)
+{
+	omap_mmc_init(1, 0, 0);
+
+	return 0;
+}
+#endif
diff --git a/board/ti/ti814x/evm.h b/board/ti/ti814x/evm.h
new file mode 100644
index 0000000..40f8710
--- /dev/null
+++ b/board/ti/ti814x/evm.h
@@ -0,0 +1,7 @@
+#ifndef _EVM_H
+#define _EVM_H
+
+void enable_uart0_pin_mux(void);
+void enable_mmc1_pin_mux(void);
+
+#endif /* _EVM_H */
diff --git a/board/ti/ti814x/mux.c b/board/ti/ti814x/mux.c
new file mode 100644
index 0000000..137acb4
--- /dev/null
+++ b/board/ti/ti814x/mux.c
@@ -0,0 +1,51 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include <i2c.h>
+#include "evm.h"
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(pincntl70), PULLUP_EN | MODE(0x01)},	/* UART0_RXD */
+	{OFFSET(pincntl71), PULLUP_EN | MODE(0x01)},	/* UART0_TXD */
+	{-1},
+};
+
+static struct module_pin_mux mmc1_pin_mux[] = {
+	{OFFSET(pincntl1), PULLUP_EN | MODE(0x01)},	/* SD1_CLK */
+	{OFFSET(pincntl2), PULLUP_EN | MODE(0x01)},	/* SD1_CMD */
+	{OFFSET(pincntl3), PULLUP_EN | MODE(0x01)},	/* SD1_DAT[0] */
+	{OFFSET(pincntl4), PULLUP_EN | MODE(0x01)},	/* SD1_DAT[1] */
+	{OFFSET(pincntl5), PULLUP_EN | MODE(0x01)},	/* SD1_DAT[2] */
+	{OFFSET(pincntl6), PULLUP_EN | MODE(0x01)},	/* SD1_DAT[3] */
+	{OFFSET(pincntl74), PULLUP_EN | MODE(0x40)},	/* SD1_POW */
+	{OFFSET(pincntl75), MODE(0x40)},		/* SD1_SDWP */
+	{OFFSET(pincntl80), PULLUP_EN | MODE(0x02)},	/* SD1_SDCD */
+	{-1},
+};
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void enable_mmc1_pin_mux(void)
+{
+	configure_module_pin_mux(mmc1_pin_mux);
+}
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
new file mode 100644
index 0000000..ca07eb2
--- /dev/null
+++ b/include/configs/ti814x_evm.h
@@ -0,0 +1,213 @@
+#define __CONFIG_TI814X_EVM_H
+
+#define CONFIG_TI81XX
+#define CONFIG_TI814X
+#define CONFIG_SYS_NO_FLASH
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/hardware.h>
+
+#define CONFIG_DMA_COHERENT
+#define CONFIG_DMA_COHERENT_SIZE	(1 << 20)
+
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
+#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* Use HUSH for command parsing */
+#define CONFIG_SYS_PROMPT		"U-Boot# "
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_MACH_TYPE		MACH_TYPE_TI8148EVM
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs  */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1	/* for ramdisk support */
+
+/* commands to include */
+# include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_VERSION_VARIABLE
+
+#define CONFIG_BOOTDELAY		1	/* negative for no autoboot */
+#define CONFIG_ENV_VARS_UBOOT_CONFIG
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x80200000\0" \
+	"fdtaddr=0x80F80000\0" \
+	"rdaddr=0x81000000\0" \
+	"bootfile=/boot/uImage\0" \
+	"fdtfile=\0" \
+	"console=ttyO0,115200n8\0" \
+	"optargs=\0" \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 ro\0" \
+	"mmcrootfstype=ext4 rootwait\0" \
+	"ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
+	"ramrootfstype=ext2\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"bootenv=uEnv.txt\0" \
+	"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t $loadaddr $filesize\0" \
+	"ramargs=setenv bootargs console=${console} " \
+		"${optargs} " \
+		"root=${ramroot} " \
+		"rootfstype=${ramrootfstype}\0" \
+	"loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
+	"loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
+	"loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"ramboot=echo Booting from ramdisk ...; " \
+		"run ramargs; " \
+		"bootm ${loadaddr}\0" \
+	"findfdt="\
+		"if test $board_name = A335BONE; then " \
+			"setenv fdtfile am335x-bone.dtb; fi; " \
+		"if test $board_name = A33515BB; then " \
+			"setenv fdtfile am335x-evm.dtb; fi; " \
+		"if test $board_name = A335X_SK; then " \
+			"setenv fdtfile am335x-evmsk.dtb; fi\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"echo SD/MMC found on device ${mmcdev};" \
+		"if run loadbootenv; then " \
+			"echo Loaded environment from ${bootenv};" \
+			"run importbootenv;" \
+		"fi;" \
+		"if test -n $uenvcmd; then " \
+			"echo Running uenvcmd ...;" \
+			"run uenvcmd;" \
+		"fi;" \
+		"if run loaduimage; then " \
+			"run mmcboot;" \
+		"fi;" \
+	"fi;" \
+
+/* Clock Defines */
+#define V_OSCK			24000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#define CONFIG_CMD_ECHO
+
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS		16
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE		512
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE \
+					+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/* memtest works on 8 MB in DRAM offset 32MB from start of ram disk*/
+#define CONFIG_SYS_MEMTEST_START	(PHYS_DRAM_1 + (64 * 1024 * 1024))
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START \
+					+ (8 * 1024 * 1024))
+
+#define CONFIG_SYS_LOAD_ADDR		0x81000000	/* Default */
+#define CONFIG_SYS_HZ			1000		/* 1ms clock */
+
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+/**
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS		1		/* 1 banks of DRAM */
+#define PHYS_DRAM_1			0x80000000	/* DRAM Bank #1 */
+#define PHYS_DRAM_1_SIZE		0x20000000	/* 512MB */
+#define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1024MB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_DRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR		(NON_SECURE_SRAM_END - \
+					 GENERATED_GBL_DATA_SIZE)
+
+/**
+ * Platform/Board specific defs
+ */
+#define CONFIG_SYS_TIMERBASE		0x4802E000
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ			1000
+
+#undef CONFIG_NAND_OMAP_GPMC
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		(48000000)
+#define CONFIG_SYS_NS16550_COM1		0x48020000	/* Base EVM has UART0 */
+
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 110, 300, 600, 1200, 2400, \
+4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
+
+#define CONFIG_ENV_OVERWRITE		1
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+#define CONFIG_ENV_IS_NOWHERE
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE		0x40300000
+#define CONFIG_SPL_MAX_SIZE		((128 - 18) * 1024)
+#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS      0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION    1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME        "u-boot.img"
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_YMODEM_SUPPORT
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
+#define CONFIG_SYS_SPI_U_BOOT_SIZE	0x40000
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+#define CONFIG_SPL_BOARD_INIT
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80800000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80800000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
+/* Since SPL did pll and ddr initialization for us,
+ * we don't need to do it twice.
+ */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+/* Unsupported features */
+#undef CONFIG_USE_IRQ
-- 
1.7.9.5

[U-Boot] [PATCH 08/10] ns16550: enable quirks for ti814x

[Matt Porter]

TI814X requires the same quirks as AM33XX to be enabled.

Signed-off-by: Matt Porter <mporter@ti.com>
---
 drivers/serial/ns16550.c |    5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 87a0917..02bc85b 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -43,7 +43,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
 
 	serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
 #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
-					defined(CONFIG_AM33XX)
+			defined(CONFIG_AM33XX) || defined(CONFIG_TI814X)
 	serial_out(0x7, &com_port->mdr1);	/* mode select reset TL16C750*/
 #endif
 	serial_out(UART_LCR_BKSE | UART_LCRVAL, (ulong)&com_port->lcr);
@@ -57,7 +57,8 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
 	serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
 	serial_out(UART_LCRVAL, &com_port->lcr);
 #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
-	defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX)
+	defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX) || \
+	defined(CONFIG_TI814X)
 
 #if defined(CONFIG_APTIX)
 	/* /13 mode so Aptix 6MHz can hit 115200 */
-- 
1.7.9.5

[U-Boot] [PATCH 09/10] ti814x_evm: enable ti814x evm build

[Matt Porter]

Enable TI814X EVM build via ti814x_evm target.

Signed-off-by: Matt Porter <mporter@ti.com>
---
 Makefile                                |    2 +-
 arch/arm/cpu/armv7/Makefile             |    2 +-
 arch/arm/cpu/armv7/omap-common/Makefile |    2 +-
 boards.cfg                              |    1 +
 spl/Makefile                            |    2 +-
 5 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/Makefile b/Makefile
index 51bd918..120ab31 100644
--- a/Makefile
+++ b/Makefile
@@ -334,7 +334,7 @@ LIBS-y += api/libapi.o
 LIBS-y += post/libpost.o
 LIBS-y += test/libtest.o
 
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),)
 LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
 endif
 
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 4fdbee4..156a5ba 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -32,7 +32,7 @@ COBJS	+= cache_v7.o
 COBJS	+= cpu.o
 COBJS	+= syslib.o
 
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20)$(CONFIG_TI814X),)
 SOBJS	+= lowlevel_init.o
 endif
 
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
index 0efc80d..55e82ba 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -36,7 +36,7 @@ COBJS	+= emif-common.o
 COBJS	+= vc.o
 endif
 
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),)
 COBJS	+= boot-common.o
 SOBJS	+= lowlevel_init.o
 endif
diff --git a/boards.cfg b/boards.cfg
index 98f7a14..0eabae9 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -236,6 +236,7 @@ am335x_evm_uart2             arm         armv7       am335x              ti
 am335x_evm_uart3             arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL4,CONS_INDEX=4
 am335x_evm_uart4             arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL5,CONS_INDEX=5
 am335x_evm_uart5             arm         armv7       am335x              ti             am33xx      am335x_evm:SERIAL6,CONS_INDEX=6
+ti814x_evm                   arm         armv7       ti814x              ti             am33xx
 highbank                     arm         armv7       highbank            -              highbank
 mx51_efikamx                 arm         armv7       mx51_efikamx        genesi         mx5		mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg
 mx51_efikasb                 arm         armv7       mx51_efikamx        genesi         mx5		mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg
diff --git a/spl/Makefile b/spl/Makefile
index 6dbb105..9761e7d 100644
--- a/spl/Makefile
+++ b/spl/Makefile
@@ -82,7 +82,7 @@ LIBS-$(CONFIG_SPL_NET_SUPPORT) += net/libnet.o
 LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/libnet.o
 LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/libphy.o
 
-ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
+ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),)
 LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
 endif
 
-- 
1.7.9.5

[U-Boot] [PATCH 10/10] MAINTAINERS: add ti814x_evm maintainer

[Matt Porter]

Add a maintainer entry for the TI814x EVM.

Signed-off-by: Matt Porter <mporter@ti.com>
---
 MAINTAINERS |    4 ++++
 1 file changed, 4 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index d3ed390..282dead 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -830,6 +830,10 @@ Stelian Pop <stelian@popies.net>
 	at91sam9263ek	ARM926EJS (AT91SAM9263 SoC)
 	at91sam9rlek	ARM926EJS (AT91SAM9RL SoC)
 
+Matt Porter <mporter@ti.com>
+
+	ti814x_evm	ARM ARMV7 (TI814x Soc)
+
 Dave Purdy <david.c.purdy@gmail.com>
 
 	pogo_e02	ARM926EJS (Kirkwood SoC)
-- 
1.7.9.5

[U-Boot] [PATCH 01/10] am33xx: convert defines from am33xx-specific to generic names

[Tom Rini]

On Wed, Feb 13, 2013 at 09:43:55AM -0500, Matt Porter wrote:

> Eliminate AM33xx specific names to prepare for TI814x support
> within AM33xx-land.
> 
> Signed-off-by: Matt Porter <mporter@ti.com>

Reviewed-by: Tom Rini <trini@ti.com>

-- 
Tom
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[U-Boot] [PATCH 02/10] am33xx: refactor emif4/ddr to support multiple EMIF instances

[Tom Rini]

On Wed, Feb 13, 2013 at 09:43:56AM -0500, Matt Porter wrote:

> The AM33xx emif4/ddr support closely matches what is need to support
> TI814x except that TI814x has two EMIF instances. Refactor all the
> emif4 helper calls and the config_ddr() init function to use an
> additional instance number argument.
> 
> Signed-off-by: Matt Porter <mporter@ti.com>

Reviewed-by: Tom Rini <trini@ti.com>

-- 
Tom
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[U-Boot] [PATCH 03/10] am33xx: refactor am33xx clocks and add ti814x support

[Tom Rini]

On Wed, Feb 13, 2013 at 09:43:57AM -0500, Matt Porter wrote:

> Split clock.c for am335x and ti814x and add the ti814x include file.
> 
> Signed-off-by: Matt Porter <mporter@ti.com>

[snip]
> +++ b/arch/arm/cpu/armv7/am33xx/clock-am335x.c
[snip]
> +#define PRCM_MOD_EN		0x2
> +#define PRCM_FORCE_WAKEUP	0x2
> +#define PRCM_FUNCTL		0x0
> +
> +#define PRCM_EMIF_CLK_ACTIVITY	BIT(2)
> +#define PRCM_L3_GCLK_ACTIVITY	BIT(4)
> +
> +#define PLL_BYPASS_MODE		0x4
> +#define ST_MN_BYPASS		0x00000100
> +#define ST_DPLL_CLK		0x00000001
> +#define CLK_SEL_MASK		0x7ffff
> +#define CLK_DIV_MASK		0x1f
> +#define CLK_DIV2_MASK		0x7f
> +#define CLK_SEL_SHIFT		0x8
> +#define CLK_MODE_SEL		0x7
> +#define CLK_MODE_MASK		0xfffffff8
> +#define CLK_DIV_SEL		0xFFFFFFE0
> +#define CPGMAC0_IDLE		0x30000
> +#define DPLL_CLKDCOLDO_GATE_CTRL        0x300
[snip]
> +++ b/arch/arm/cpu/armv7/am33xx/clock-ti814x.c
[snip]
> +	/* Selects OSC0 (20MHz) for DMTIMER1 */
> +	temp = readl(DMTIMER_CLKSRC);
> +	temp &= ~(0x7 << 3);
> +	temp |= (0x4 << 3);
> +	writel(temp, DMTIMER_CLKSRC);
> +
> +	writel(0x2, DM_TIMER1_BASE + 0x54);

Magic values are defined for clock-am335x.c but not in clock-ti814x.c,
please fix clock-ti814x.c to define out the magic values ala am335x.c.
Thanks!

-- 
Tom
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[U-Boot] [PATCH 04/10] am33xx: refactor am33xx mux support and add ti814x support

[Tom Rini]

On Wed, Feb 13, 2013 at 09:43:58AM -0500, Matt Porter wrote:

> AM33XX and TI814X have a similar mux though the pinmux register
> layout and address space differ. Add a separate ti814x mux include
> to support the TI814X-specific differences.
> 
> Signed-off-by: Matt Porter <mporter@ti.com>

Reviewed-by: Tom Rini <trini@ti.com>

-- 
Tom
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[U-Boot] [PATCH 05/10] am33xx: add ti814x specific register definitions

[Tom Rini]

On Wed, Feb 13, 2013 at 09:43:59AM -0500, Matt Porter wrote:

> Support the ti814x specific register definitions within
> arch-am33xx.
> 
> Signed-off-by: Matt Porter <mporter@ti.com>

Reviewed-by: Tom Rini <trini@ti.com>

-- 
Tom
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[U-Boot] [PATCH 06/10] am33xx: add dmm support to emif4 library

[Tom Rini]

On Wed, Feb 13, 2013 at 09:44:00AM -0500, Matt Porter wrote:

> Adds a config_dmm() routine to support TI814X DMM configuration.
> 
> Signed-off-by: Matt Porter <mporter@ti.com>

Reviewed-by: Tom Rini <trini@ti.com>

-- 
Tom
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[U-Boot] [PATCH 07/10] ti814x_evm: add ti814x evm board support

[Tom Rini]

On Wed, Feb 13, 2013 at 09:44:01AM -0500, Matt Porter wrote:

> Add TI814X EVM board directory and config file.
> 
> Signed-off-by: Matt Porter <mporter@ti.com>
[snip]
> +++ b/board/ti/ti814x/evm.h
> @@ -0,0 +1,7 @@
> +#ifndef _EVM_H
[snip]
> +++ b/include/configs/ti814x_evm.h
> @@ -0,0 +1,213 @@
> +#define __CONFIG_TI814X_EVM_H

Needs GPLv2 or later boilerplate.

[snip]
> +#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs  */
> +#define CONFIG_SETUP_MEMORY_TAGS	1
> +#define CONFIG_INITRD_TAG		1	/* for ramdisk support */

Just #define CONFIG_FOO in these cases (and some others that follow)

[snip]
> +	"findfdt="\
> +		"if test $board_name = A335BONE; then " \
> +			"setenv fdtfile am335x-bone.dtb; fi; " \
> +		"if test $board_name = A33515BB; then " \
> +			"setenv fdtfile am335x-evm.dtb; fi; " \
> +		"if test $board_name = A335X_SK; then " \
> +			"setenv fdtfile am335x-evmsk.dtb; fi\0" \

That's not right :)

[snip]
> +/* memtest works on 8 MB in DRAM offset 32MB from start of ram disk*/
> +#define CONFIG_SYS_MEMTEST_START	(PHYS_DRAM_1 + (64 * 1024 * 1024))
> +#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START \
> +					+ (8 * 1024 * 1024))

This isn't your mistake initially, but this should just be start of
memory to smallest possible config the evm can come with - 4MB.

[snip]
> +#undef CONFIG_NAND_OMAP_GPMC

Just leave it out.

> +#define CONFIG_SYS_BAUDRATE_TABLE	{ 110, 300, 600, 1200, 2400, \
> +4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }

Leave that out and get the generic table.  am335x needs to be updated
for that.

[snip]
> +/* Since SPL did pll and ddr initialization for us,
> + * we don't need to do it twice.
> + */

/*
 * Must be like
 * this.
 */

-- 
Tom
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[U-Boot] [PATCH 08/10] ns16550: enable quirks for ti814x

[Tom Rini]

On Wed, Feb 13, 2013 at 09:44:02AM -0500, Matt Porter wrote:

> TI814X requires the same quirks as AM33XX to be enabled.
> 
> Signed-off-by: Matt Porter <mporter@ti.com>

Reviewed-by: Tom Rini <trini@ti.com>

-- 
Tom
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[U-Boot] [PATCH 09/10] ti814x_evm: enable ti814x evm build

[Tom Rini]

On Wed, Feb 13, 2013 at 09:44:03AM -0500, Matt Porter wrote:

> Enable TI814X EVM build via ti814x_evm target.
> 
> Signed-off-by: Matt Porter <mporter@ti.com>

This should just get squashed into the patch that adds the board code.
Otherwise,

Reviewed-by: Tom Rini <trini@ti.com>

-- 
Tom
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[U-Boot] [PATCH 10/10] MAINTAINERS: add ti814x_evm maintainer

[Tom Rini]

On Wed, Feb 13, 2013 at 09:44:04AM -0500, Matt Porter wrote:

> Add a maintainer entry for the TI814x EVM.
> 
> Signed-off-by: Matt Porter <mporter@ti.com>

Please squash this into the patch which adds the EVM, thanks.

-- 
Tom
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[U-Boot] [PATCH 03/10] am33xx: refactor am33xx clocks and add ti814x support

[Matt Porter]

On Fri, Feb 15, 2013 at 04:37:33PM +0000, Tom Rini wrote:
> On Wed, Feb 13, 2013 at 09:43:57AM -0500, Matt Porter wrote:
> 
> > Split clock.c for am335x and ti814x and add the ti814x include file.
> > 
> > Signed-off-by: Matt Porter <mporter@ti.com>
> 
> [snip]
> > +++ b/arch/arm/cpu/armv7/am33xx/clock-am335x.c
> [snip]
> > +#define PRCM_MOD_EN		0x2
> > +#define PRCM_FORCE_WAKEUP	0x2
> > +#define PRCM_FUNCTL		0x0
> > +
> > +#define PRCM_EMIF_CLK_ACTIVITY	BIT(2)
> > +#define PRCM_L3_GCLK_ACTIVITY	BIT(4)
> > +
> > +#define PLL_BYPASS_MODE		0x4
> > +#define ST_MN_BYPASS		0x00000100
> > +#define ST_DPLL_CLK		0x00000001
> > +#define CLK_SEL_MASK		0x7ffff
> > +#define CLK_DIV_MASK		0x1f
> > +#define CLK_DIV2_MASK		0x7f
> > +#define CLK_SEL_SHIFT		0x8
> > +#define CLK_MODE_SEL		0x7
> > +#define CLK_MODE_MASK		0xfffffff8
> > +#define CLK_DIV_SEL		0xFFFFFFE0
> > +#define CPGMAC0_IDLE		0x30000
> > +#define DPLL_CLKDCOLDO_GATE_CTRL        0x300
> [snip]
> > +++ b/arch/arm/cpu/armv7/am33xx/clock-ti814x.c
> [snip]
> > +	/* Selects OSC0 (20MHz) for DMTIMER1 */
> > +	temp = readl(DMTIMER_CLKSRC);
> > +	temp &= ~(0x7 << 3);
> > +	temp |= (0x4 << 3);
> > +	writel(temp, DMTIMER_CLKSRC);
> > +
> > +	writel(0x2, DM_TIMER1_BASE + 0x54);
> 
> Magic values are defined for clock-am335x.c but not in clock-ti814x.c,
> please fix clock-ti814x.c to define out the magic values ala am335x.c.
> Thanks!

Ok, will clean this up.

-Matt

[U-Boot] [PATCH 07/10] ti814x_evm: add ti814x evm board support

[Matt Porter]

On Fri, Feb 15, 2013 at 04:38:22PM +0000, Tom Rini wrote:
> On Wed, Feb 13, 2013 at 09:44:01AM -0500, Matt Porter wrote:
> 
> > Add TI814X EVM board directory and config file.
> > 
> > Signed-off-by: Matt Porter <mporter@ti.com>
> [snip]
> > +++ b/board/ti/ti814x/evm.h
> > @@ -0,0 +1,7 @@
> > +#ifndef _EVM_H
> [snip]
> > +++ b/include/configs/ti814x_evm.h
> > @@ -0,0 +1,213 @@
> > +#define __CONFIG_TI814X_EVM_H
> 
> Needs GPLv2 or later boilerplate.

Ok.

> 
> [snip]
> > +#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs  */
> > +#define CONFIG_SETUP_MEMORY_TAGS	1
> > +#define CONFIG_INITRD_TAG		1	/* for ramdisk support */
> 
> Just #define CONFIG_FOO in these cases (and some others that follow)

Ok.
> 
> [snip]
> > +	"findfdt="\
> > +		"if test $board_name = A335BONE; then " \
> > +			"setenv fdtfile am335x-bone.dtb; fi; " \
> > +		"if test $board_name = A33515BB; then " \
> > +			"setenv fdtfile am335x-evm.dtb; fi; " \
> > +		"if test $board_name = A335X_SK; then " \
> > +			"setenv fdtfile am335x-evmsk.dtb; fi\0" \
> 
> That's not right :)

LOL, indeed..forgot about that am335x specific stuff. Will fix.

> [snip]
> > +/* memtest works on 8 MB in DRAM offset 32MB from start of ram disk*/
> > +#define CONFIG_SYS_MEMTEST_START	(PHYS_DRAM_1 + (64 * 1024 * 1024))
> > +#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START \
> > +					+ (8 * 1024 * 1024))
> 
> This isn't your mistake initially, but this should just be start of
> memory to smallest possible config the evm can come with - 4MB.

Ok.

> 
> [snip]
> > +#undef CONFIG_NAND_OMAP_GPMC
> 
> Just leave it out.

Ok.

> > +#define CONFIG_SYS_BAUDRATE_TABLE	{ 110, 300, 600, 1200, 2400, \
> > +4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
> 
> Leave that out and get the generic table.  am335x needs to be updated
> for that.

Ok, will do. I even saw something about this and forgot to update this
config.

> [snip]
> > +/* Since SPL did pll and ddr initialization for us,
> > + * we don't need to do it twice.
> > + */
> 
> /*
>  * Must be like
>  * this.
>  */

Ok.

[U-Boot] [PATCH 09/10] ti814x_evm: enable ti814x evm build

[Matt Porter]

On Fri, Feb 15, 2013 at 11:39:01AM -0500, Tom Rini wrote:
> On Wed, Feb 13, 2013 at 09:44:03AM -0500, Matt Porter wrote:
> 
> > Enable TI814X EVM build via ti814x_evm target.
> > 
> > Signed-off-by: Matt Porter <mporter@ti.com>
> 
> This should just get squashed into the patch that adds the board code.
> Otherwise,
> 
> Reviewed-by: Tom Rini <trini@ti.com>

Sounds good. I'll squash it in there.

-Matt

[U-Boot] [PATCH 10/10] MAINTAINERS: add ti814x_evm maintainer

[Matt Porter]

On Fri, Feb 15, 2013 at 11:39:13AM -0500, Tom Rini wrote:
> On Wed, Feb 13, 2013 at 09:44:04AM -0500, Matt Porter wrote:
> 
> > Add a maintainer entry for the TI814x EVM.
> > 
> > Signed-off-by: Matt Porter <mporter@ti.com>
> 
> Please squash this into the patch which adds the EVM, thanks.

Will do, thanks for the review.

-Matt

[U-Boot] [PATCH 03/10] am33xx: refactor am33xx clocks and add ti814x support

[Peter Korsgaard]

>>>>> "Matt" == Matt Porter <mporter@ti.com> writes:

 Matt> Split clock.c for am335x and ti814x and add the ti814x include file.
 Matt> Signed-off-by: Matt Porter <mporter@ti.com>
 Matt> ---
 Matt>  arch/arm/cpu/armv7/am33xx/Makefile               |    3 +-
 Matt>  arch/arm/cpu/armv7/am33xx/clock-am335x.c         |  374 ++++++++++++++++++++++
 Matt>  arch/arm/cpu/armv7/am33xx/clock-ti814x.c         |  234 ++++++++++++++
 Matt>  arch/arm/cpu/armv7/am33xx/clock.c                |  374 ----------------------
 Matt>  arch/arm/include/asm/arch-am33xx/clock.h         |    4 +
 Matt>  arch/arm/include/asm/arch-am33xx/clocks_ti814x.h |  112 +++++++
 Matt>  6 files changed, 726 insertions(+), 375 deletions(-)
 Matt>  create mode 100644 arch/arm/cpu/armv7/am33xx/clock-am335x.c
 Matt>  create mode 100644 arch/arm/cpu/armv7/am33xx/clock-ti814x.c
 Matt>  delete mode 100644 arch/arm/cpu/armv7/am33xx/clock.c
 Matt>  create mode 100644 arch/arm/include/asm/arch-am33xx/clocks_ti814x.h

Do you have rename detection enabled? I would have imagined
clock-am335x.c to show up as a copy of clock.c

 Matt> +++ b/arch/arm/cpu/armv7/am33xx/clock-am335x.c
 Matt> @@ -0,0 +1,374 @@
 Matt> +/*
 Matt> + * clock.c
 Matt> + *
 Matt> + * clocks for AM33XX based boards
 Matt> + *
 Matt> + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/

This is no longer clock.c or 2011. Care to update the header?

 Matt> +++ b/arch/arm/cpu/armv7/am33xx/clock-ti814x.c
 Matt> @@ -0,0 +1,234 @@
 Matt> +/*
 Matt> + * clock.c
 Matt> + *
 Matt> + * clocks for TI814X based boards
 Matt> + *
 Matt> + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/

Same here.

-- 
Bye, Peter Korsgaard

[U-Boot] [PATCH 04/10] am33xx: refactor am33xx mux support and add ti814x support

[Peter Korsgaard]

>>>>> "Matt" == Matt Porter <mporter@ti.com> writes:

 Matt> AM33XX and TI814X have a similar mux though the pinmux register
 Matt> layout and address space differ. Add a separate ti814x mux include
 Matt> to support the TI814X-specific differences.

Same comment about the file headers as patch 03, otherwise it looks
good.

Acked-by: Peter Korsgaard <jacmet@sunsite.dk>

-- 
Bye, Peter Korsgaard

[U-Boot] [PATCH 05/10] am33xx: add ti814x specific register definitions

[Peter Korsgaard]

>>>>> "Matt" == Matt Porter <mporter@ti.com> writes:

 Matt> Support the ti814x specific register definitions within
 Matt> arch-am33xx.

 Matt> Signed-off-by: Matt Porter <mporter@ti.com>
 Matt> ---
 Matt>  arch/arm/cpu/armv7/am33xx/sys_info.c        |    3 +++
 Matt>  arch/arm/include/asm/arch-am33xx/cpu.h      |   11 +++++----
 Matt>  arch/arm/include/asm/arch-am33xx/hardware.h |   32 +++++++++++++++++++++++++++
 Matt>  arch/arm/include/asm/arch-am33xx/omap.h     |    7 ++++++
 Matt>  arch/arm/include/asm/arch-am33xx/spl.h      |    5 +++++
 Matt>  5 files changed, 54 insertions(+), 4 deletions(-)
 
 Matt> diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
 Matt> index 41ab2c0..786c159 100644
 Matt> --- a/arch/arm/include/asm/arch-am33xx/hardware.h
 Matt> +++ b/arch/arm/include/asm/arch-am33xx/hardware.h
 Matt> @@ -20,9 +20,14 @@
 Matt>  #define __AM33XX_HARDWARE_H
 
 Matt>  #include <asm/arch/omap.h>
 Matt> +#include <config.h>

Quite some of the base addresses are similar, but I wonder if it
wouldn't be cleaner to simply have a hardware-am33xx.h /
hardware-ti814x.h instead of all these ifdef / elif?
 
 Matt>  /* Control Module Base Address */
 Matt> +#ifdef CONFIG_AM33XX
 Matt>  #define CTRL_BASE			0x44E10000
 Matt>  #define CTRL_DEVICE_BASE		0x44E10600
 Matt> +#elif defined(CONFIG_TI814X)
 Matt> +#define CTRL_BASE			0x48140000
 Matt> +#endif

No CTRL_DEVICE_BASE on ti814x?


 Matt> --- a/arch/arm/include/asm/arch-am33xx/spl.h
 Matt> +++ b/arch/arm/include/asm/arch-am33xx/spl.h
 Matt> @@ -25,8 +25,13 @@
 
 Matt>  #define BOOT_DEVICE_XIP       	2
 Matt>  #define BOOT_DEVICE_NAND	5
 Matt> +#ifdef CONFIG_AM33XX
 Matt>  #define BOOT_DEVICE_MMC1	8
 Matt>  #define BOOT_DEVICE_MMC2	9	/* eMMC or daughter card */
 Matt> +#elif defined(CONFIG_TI814X)
 Matt> +#define BOOT_DEVICE_MMC1	9
 Matt> +#define BOOT_DEVICE_MMC2	8	/* ROM only supports 2nd instance */

Argh! Couldn't we just swap the meaning of mmc1/mmc2 or would that be
too confusing?

 Matt> +#endif
 Matt>  #define BOOT_DEVICE_SPI		11
 Matt>  #define BOOT_DEVICE_UART	65
 Matt>  #define BOOT_DEVICE_CPGMAC	70
 Matt> -- 
 Matt> 1.7.9.5

 Matt> _______________________________________________
 Matt> U-Boot mailing list
 Matt> U-Boot at lists.denx.de
 Matt> http://lists.denx.de/mailman/listinfo/u-boot


-- 
Bye, Peter Korsgaard

[U-Boot] [PATCH 05/10] am33xx: add ti814x specific register definitions

[Tom Rini]

On Sun, Feb 17, 2013 at 09:28:33PM +0100, Peter Korsgaard wrote:
> >>>>> "Matt" == Matt Porter <mporter@ti.com> writes:
> 
>  Matt> Support the ti814x specific register definitions within
>  Matt> arch-am33xx.
> 
>  Matt> Signed-off-by: Matt Porter <mporter@ti.com>
>  Matt> ---
>  Matt>  arch/arm/cpu/armv7/am33xx/sys_info.c        |    3 +++
>  Matt>  arch/arm/include/asm/arch-am33xx/cpu.h      |   11 +++++----
>  Matt>  arch/arm/include/asm/arch-am33xx/hardware.h |   32 +++++++++++++++++++++++++++
>  Matt>  arch/arm/include/asm/arch-am33xx/omap.h     |    7 ++++++
>  Matt>  arch/arm/include/asm/arch-am33xx/spl.h      |    5 +++++
>  Matt>  5 files changed, 54 insertions(+), 4 deletions(-)
>  
>  Matt> diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
>  Matt> index 41ab2c0..786c159 100644
>  Matt> --- a/arch/arm/include/asm/arch-am33xx/hardware.h
>  Matt> +++ b/arch/arm/include/asm/arch-am33xx/hardware.h
>  Matt> @@ -20,9 +20,14 @@
>  Matt>  #define __AM33XX_HARDWARE_H
>  
>  Matt>  #include <asm/arch/omap.h>
>  Matt> +#include <config.h>
> 
> Quite some of the base addresses are similar, but I wonder if it
> wouldn't be cleaner to simply have a hardware-am33xx.h /
> hardware-ti814x.h instead of all these ifdef / elif?

Since I suspect the things common from ti814x and am33xx are also common
to ti816x (which has been left as an exercise to whomever needs that
next), I think we can re-structure this into something like that, but
keeping the common parts within hardware.h still.

>  Matt>  /* Control Module Base Address */
>  Matt> +#ifdef CONFIG_AM33XX
>  Matt>  #define CTRL_BASE			0x44E10000
>  Matt>  #define CTRL_DEVICE_BASE		0x44E10600
>  Matt> +#elif defined(CONFIG_TI814X)
>  Matt> +#define CTRL_BASE			0x48140000
>  Matt> +#endif
> 
> No CTRL_DEVICE_BASE on ti814x?

I think this is a side-effect of Matt not supporting the things attached
to it (USB in the case of am335x).

>  Matt> --- a/arch/arm/include/asm/arch-am33xx/spl.h
>  Matt> +++ b/arch/arm/include/asm/arch-am33xx/spl.h
>  Matt> @@ -25,8 +25,13 @@
>  
>  Matt>  #define BOOT_DEVICE_XIP       	2
>  Matt>  #define BOOT_DEVICE_NAND	5
>  Matt> +#ifdef CONFIG_AM33XX
>  Matt>  #define BOOT_DEVICE_MMC1	8
>  Matt>  #define BOOT_DEVICE_MMC2	9	/* eMMC or daughter card */
>  Matt> +#elif defined(CONFIG_TI814X)
>  Matt> +#define BOOT_DEVICE_MMC1	9
>  Matt> +#define BOOT_DEVICE_MMC2	8	/* ROM only supports 2nd instance */
> 
> Argh! Couldn't we just swap the meaning of mmc1/mmc2 or would that be
> too confusing?

IMHO, that will lead to further confusion down the line.  I talked with
Matt about this before and well, it's funky.

-- 
Tom
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[U-Boot] [PATCH 05/10] am33xx: add ti814x specific register definitions

[Peter Korsgaard]

>>>>> "Tom" == Tom Rini <trini@ti.com> writes:

Hi,

 >> Quite some of the base addresses are similar, but I wonder if it
 >> wouldn't be cleaner to simply have a hardware-am33xx.h /
 >> hardware-ti814x.h instead of all these ifdef / elif?

 Tom> Since I suspect the things common from ti814x and am33xx are also common
 Tom> to ti816x (which has been left as an exercise to whomever needs that
 Tom> next), I think we can re-structure this into something like that, but
 Tom> keeping the common parts within hardware.h still.

FYI, I might very well be that guy as I've recently started work on a
ti816x based project.

 >> Argh! Couldn't we just swap the meaning of mmc1/mmc2 or would that be
 >> too confusing?

 Tom> IMHO, that will lead to further confusion down the line.  I talked with
 Tom> Matt about this before and well, it's funky.

Ok.

-- 
Bye, Peter Korsgaard

[U-Boot] [PATCH 05/10] am33xx: add ti814x specific register definitions

[Brian Hutchinson]

I need ti816x u-boot too!  Maybe I can help too. Need 3.x kernel too but I
guess that is for another list :)

Regards,

Brian

On Feb 18, 2013 7:21 AM, "Peter Korsgaard" <jacmet@sunsite.dk> wrote:
>
> >>>>> "Tom" == Tom Rini <trini@ti.com> writes:
>
> Hi,
>
>  >> Quite some of the base addresses are similar, but I wonder if it
>  >> wouldn't be cleaner to simply have a hardware-am33xx.h /
>  >> hardware-ti814x.h instead of all these ifdef / elif?
>
>  Tom> Since I suspect the things common from ti814x and am33xx are also
common
>  Tom> to ti816x (which has been left as an exercise to whomever needs that
>  Tom> next), I think we can re-structure this into something like that,
but
>  Tom> keeping the common parts within hardware.h still.
>
> FYI, I might very well be that guy as I've recently started work on a
> ti816x based project.
>
>  >> Argh! Couldn't we just swap the meaning of mmc1/mmc2 or would that be
>  >> too confusing?
>
>  Tom> IMHO, that will lead to further confusion down the line.  I talked
with
>  Tom> Matt about this before and well, it's funky.
>
> Ok.
>
> --
> Bye, Peter Korsgaard
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 05/10] am33xx: add ti814x specific register definitions

[Peter Korsgaard]

>>>>> "Brian" == Brian Hutchinson <b.hutchman@gmail.com> writes:

Hi,

 Brian> I need ti816x u-boot too!? Maybe I can help too. Need 3.x kernel
 Brian> too but I guess that is for another list :)

Antoine is working on it, and the basics are running:

U-Boot SPL 2013.01-00297-gf592f9c-dirty (Feb 22 2013 - 16:25:01)
OMAP SD/MMC: 0
boot mode - FAT
reading u-boot.img
reading u-boot.img


U-Boot 2013.01-00297-gf592f9c-dirty (Feb 22 2013 - 16:25:01)

AMTI81XX-GP rev 1
DRAM:  1 GiB
WARNING: Caches not enabled
MMC:   OMAP SD/MMC: 0
Using default environment

Net:   DaVinci-EMAC
Hit any key to stop autoboot:  0

I'm looking at the emac driver at the moment. It still needs some more
work and cleanup, but I would imagine an early series could be posted
next week or so is Antoine agrees.

-- 
Bye, Peter Korsgaard

[U-Boot] [PATCH 05/10] am33xx: add ti814x specific register definitions

[Tom Rini]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

On 02/22/2013 10:37 AM, Peter Korsgaard wrote:
>>>>>> "Brian" == Brian Hutchinson <b.hutchman@gmail.com>
>>>>>> writes:
> 
> Hi,
> 
> Brian> I need ti816x u-boot too!  Maybe I can help too. Need 3.x
> kernel Brian> too but I guess that is for another list :)
> 
> Antoine is working on it, and the basics are running:
> 
> U-Boot SPL 2013.01-00297-gf592f9c-dirty (Feb 22 2013 - 16:25:01) 
> OMAP SD/MMC: 0 boot mode - FAT reading u-boot.img reading
> u-boot.img
> 
> 
> U-Boot 2013.01-00297-gf592f9c-dirty (Feb 22 2013 - 16:25:01)
> 
> AMTI81XX-GP rev 1 DRAM:  1 GiB WARNING: Caches not enabled MMC:
> OMAP SD/MMC: 0 Using default environment
> 
> Net:   DaVinci-EMAC Hit any key to stop autoboot:  0
> 
> I'm looking at the emac driver at the moment. It still needs some
> more work and cleanup, but I would imagine an early series could be
> posted next week or so is Antoine agrees.

Can we please make the emac driver switch to phylib while you're in
there?  Thanks!

- -- 
Tom
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[U-Boot] [PATCH 05/10] am33xx: add ti814x specific register definitions

[Peter Korsgaard]

>>>>> "Tom" == Tom Rini <trini@ti.com> writes:

Hi,

 >> I'm looking at the emac driver at the moment. It still needs some
 >> more work and cleanup, but I would imagine an early series could be
 >> posted next week or so is Antoine agrees.

 Tom> Can we please make the emac driver switch to phylib while you're
 Tom> in there?  Thanks!

I can have a look, but I don't have access to any of the older devices
using the driver.

-- 
Bye, Peter Korsgaard

[U-Boot] [PATCH 03/10] am33xx: refactor am33xx clocks and add ti814x support

[Matt Porter]

On Sun, Feb 17, 2013 at 09:17:01PM +0100, Peter Korsgaard wrote:
> >>>>> "Matt" == Matt Porter <mporter@ti.com> writes:
> 
>  Matt> Split clock.c for am335x and ti814x and add the ti814x include file.
>  Matt> Signed-off-by: Matt Porter <mporter@ti.com>
>  Matt> ---
>  Matt>  arch/arm/cpu/armv7/am33xx/Makefile               |    3 +-
>  Matt>  arch/arm/cpu/armv7/am33xx/clock-am335x.c         |  374 ++++++++++++++++++++++
>  Matt>  arch/arm/cpu/armv7/am33xx/clock-ti814x.c         |  234 ++++++++++++++
>  Matt>  arch/arm/cpu/armv7/am33xx/clock.c                |  374 ----------------------
>  Matt>  arch/arm/include/asm/arch-am33xx/clock.h         |    4 +
>  Matt>  arch/arm/include/asm/arch-am33xx/clocks_ti814x.h |  112 +++++++
>  Matt>  6 files changed, 726 insertions(+), 375 deletions(-)
>  Matt>  create mode 100644 arch/arm/cpu/armv7/am33xx/clock-am335x.c
>  Matt>  create mode 100644 arch/arm/cpu/armv7/am33xx/clock-ti814x.c
>  Matt>  delete mode 100644 arch/arm/cpu/armv7/am33xx/clock.c
>  Matt>  create mode 100644 arch/arm/include/asm/arch-am33xx/clocks_ti814x.h

Hi Peter...thanks for reviewing this.

> Do you have rename detection enabled? I would have imagined
> clock-am335x.c to show up as a copy of clock.c

On any given day I forget to format-patch with rename detection enabled.
You caught me...will be fixed in v2.

>  Matt> +++ b/arch/arm/cpu/armv7/am33xx/clock-am335x.c
>  Matt> @@ -0,0 +1,374 @@
>  Matt> +/*
>  Matt> + * clock.c
>  Matt> + *
>  Matt> + * clocks for AM33XX based boards
>  Matt> + *
>  Matt> + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
> 
> This is no longer clock.c or 2011. Care to update the header?

Ok

> 
>  Matt> +++ b/arch/arm/cpu/armv7/am33xx/clock-ti814x.c
>  Matt> @@ -0,0 +1,234 @@
>  Matt> +/*
>  Matt> + * clock.c
>  Matt> + *
>  Matt> + * clocks for TI814X based boards
>  Matt> + *
>  Matt> + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
> 
> Same here.

Ok

-Matt

[U-Boot] [PATCH 04/10] am33xx: refactor am33xx mux support and add ti814x support

[Matt Porter]

On Sun, Feb 17, 2013 at 08:18:57PM +0000, Peter Korsgaard wrote:
> >>>>> "Matt" == Matt Porter <mporter@ti.com> writes:
> 
>  Matt> AM33XX and TI814X have a similar mux though the pinmux register
>  Matt> layout and address space differ. Add a separate ti814x mux include
>  Matt> to support the TI814X-specific differences.
> 
> Same comment about the file headers as patch 03, otherwise it looks
> good.

Will clean the headers.

-Matt

> Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
> 
> -- 
> Bye, Peter Korsgaard

[U-Boot] [PATCH 05/10] am33xx: add ti814x specific register definitions

[Matt Porter]

On Mon, Feb 18, 2013 at 03:18:42PM +0000, Tom Rini wrote:
> On Sun, Feb 17, 2013 at 09:28:33PM +0100, Peter Korsgaard wrote:
> > >>>>> "Matt" == Matt Porter <mporter@ti.com> writes:
> > 
> >  Matt> Support the ti814x specific register definitions within
> >  Matt> arch-am33xx.
> > 
> >  Matt> Signed-off-by: Matt Porter <mporter@ti.com>
> >  Matt> ---
> >  Matt>  arch/arm/cpu/armv7/am33xx/sys_info.c        |    3 +++
> >  Matt>  arch/arm/include/asm/arch-am33xx/cpu.h      |   11 +++++----
> >  Matt>  arch/arm/include/asm/arch-am33xx/hardware.h |   32 +++++++++++++++++++++++++++
> >  Matt>  arch/arm/include/asm/arch-am33xx/omap.h     |    7 ++++++
> >  Matt>  arch/arm/include/asm/arch-am33xx/spl.h      |    5 +++++
> >  Matt>  5 files changed, 54 insertions(+), 4 deletions(-)
> >  
> >  Matt> diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
> >  Matt> index 41ab2c0..786c159 100644
> >  Matt> --- a/arch/arm/include/asm/arch-am33xx/hardware.h
> >  Matt> +++ b/arch/arm/include/asm/arch-am33xx/hardware.h
> >  Matt> @@ -20,9 +20,14 @@
> >  Matt>  #define __AM33XX_HARDWARE_H
> >  
> >  Matt>  #include <asm/arch/omap.h>
> >  Matt> +#include <config.h>
> > 
> > Quite some of the base addresses are similar, but I wonder if it
> > wouldn't be cleaner to simply have a hardware-am33xx.h /
> > hardware-ti814x.h instead of all these ifdef / elif?
> 
> Since I suspect the things common from ti814x and am33xx are also common
> to ti816x (which has been left as an exercise to whomever needs that
> next), I think we can re-structure this into something like that, but
> keeping the common parts within hardware.h still.

Sounds good. I'll restructure with only the common parts in hardware.h.

> >  Matt>  /* Control Module Base Address */
> >  Matt> +#ifdef CONFIG_AM33XX
> >  Matt>  #define CTRL_BASE			0x44E10000
> >  Matt>  #define CTRL_DEVICE_BASE		0x44E10600
> >  Matt> +#elif defined(CONFIG_TI814X)
> >  Matt> +#define CTRL_BASE			0x48140000
> >  Matt> +#endif
> > 
> > No CTRL_DEVICE_BASE on ti814x?
> 
> I think this is a side-effect of Matt not supporting the things attached
> to it (USB in the case of am335x).

I tried to avoid defining things I'm not yet using. For CTRL_DEVICE_BASE,
I would add it once I get to adding cpsw support as we need to read the
efused macid value from that area.

> >  Matt> --- a/arch/arm/include/asm/arch-am33xx/spl.h
> >  Matt> +++ b/arch/arm/include/asm/arch-am33xx/spl.h
> >  Matt> @@ -25,8 +25,13 @@
> >  
> >  Matt>  #define BOOT_DEVICE_XIP       	2
> >  Matt>  #define BOOT_DEVICE_NAND	5
> >  Matt> +#ifdef CONFIG_AM33XX
> >  Matt>  #define BOOT_DEVICE_MMC1	8
> >  Matt>  #define BOOT_DEVICE_MMC2	9	/* eMMC or daughter card */
> >  Matt> +#elif defined(CONFIG_TI814X)
> >  Matt> +#define BOOT_DEVICE_MMC1	9
> >  Matt> +#define BOOT_DEVICE_MMC2	8	/* ROM only supports 2nd instance */
> > 
> > Argh! Couldn't we just swap the meaning of mmc1/mmc2 or would that be
> > too confusing?
> 
> IMHO, that will lead to further confusion down the line.  I talked with
> Matt about this before and well, it's funky.

This is definitely a quirky area wrt TI814x. AFAIK it's the only
OMAP-ish part where the ROM only allows boot from a single MMC instance.
Further, that single MMC instance is actually the 2nd one as noted in
the comment. This means to keep all the existing SPL mmc init logic
intact, we need to define as above so that the unimplemented first MMC
instance (which does exist on the part) does not get intialized when the
ROM drops a bootdevice of "8".

-Matt