From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 15/26] drm/i915: add media well to VLV force wake routines Date: Wed, 6 Mar 2013 20:52:43 +0200 Message-ID: <20130306185243.GJ4469@intel.com> References: <1362175722-9281-1-git-send-email-jbarnes@virtuousgeek.org> <1362175722-9281-15-git-send-email-jbarnes@virtuousgeek.org> <20130306182807.GH4469@intel.com> <20130306103334.2651de83@jbarnes-desktop> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id AE210E67B7 for ; Wed, 6 Mar 2013 10:52:46 -0800 (PST) Content-Disposition: inline In-Reply-To: <20130306103334.2651de83@jbarnes-desktop> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Mar 06, 2013 at 10:33:34AM -0800, Jesse Barnes wrote: > On Wed, 6 Mar 2013 20:28:07 +0200 > Ville Syrj=E4l=E4 wrote: > = > > On Fri, Mar 01, 2013 at 02:08:31PM -0800, Jesse Barnes wrote: > > > We could split this out into a separate routine at some point as an > > > optimization. > > = > > BTW did anyone try to gang wakeup thing instead? > = > Not afaik. > = > > = > > > = > > > Signed-off-by: Jesse Barnes > > > --- > > > drivers/gpu/drm/i915/i915_reg.h | 2 ++ > > > drivers/gpu/drm/i915/intel_pm.c | 11 ++++++++--- > > > 2 files changed, 10 insertions(+), 3 deletions(-) > > > = > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i= 915_reg.h > > > index 1c6e066..558c6d1 100644 > > > --- a/drivers/gpu/drm/i915/i915_reg.h > > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > > @@ -4271,6 +4271,8 @@ > > > #define FORCEWAKE 0xA18C > > > #define FORCEWAKE_VLV 0x1300b0 > > > #define FORCEWAKE_ACK_VLV 0x1300b4 > > > +#define FORCEWAKE_MEDIA_VLV 0x1300b8 > > > +#define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc > > > #define FORCEWAKE_ACK_HSW 0x130044 > > > #define FORCEWAKE_ACK 0x130090 > > > #define VLV_GTLC_WAKE_CTRL 0x130090 > > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/i= ntel_pm.c > > > index 3e976f4..e3947cb 100644 > > > --- a/drivers/gpu/drm/i915/intel_pm.c > > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > > @@ -4423,10 +4423,15 @@ static void vlv_force_wake_get(struct drm_i91= 5_private *dev_priv) > > > DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); > > > = > > > I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERN= EL)); > > > + I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV, _MASKED_BIT_ENABLE(FORCEWAK= E_KERNEL)); > > > = > > > if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1), > > > FORCEWAKE_ACK_TIMEOUT_MS)) > > > - DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); > > > + DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n"); > > > + > > > + if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_MEDIA_VLV) & 1= ), > > > + FORCEWAKE_ACK_TIMEOUT_MS)) > > > + DRM_ERROR("Timed out waiting for media to ack forcewake request.\n= "); > > = > > Based on some of my recent patches the '& 1's should be > > '& FORCEWAKE_KERNEL'. > = > And that was based on my misunderstanding of MT forcewake. I thought > it was so the BIOS or AMT could do forcewake, but it's actually meant > for multiple kernel thread accesses. Since we don't do that, simply > using the lowest bit all the time is fine. I just want to be consistent which names we give the bits to avoid confusing people (mainly myself), that's all. > > > __gen6_gt_wait_for_thread_c0(dev_priv); > > > } > > > @@ -4434,8 +4439,8 @@ static void vlv_force_wake_get(struct drm_i915_= private *dev_priv) > > > static void vlv_force_wake_put(struct drm_i915_private *dev_priv) > > > { > > > I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KER= NEL)); > > > - /* something from same cacheline, but !FORCEWAKE_VLV */ > > > - POSTING_READ(FORCEWAKE_ACK_VLV); > > > + I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV, _MASKED_BIT_DISABLE(FORCEWA= KE_KERNEL)); > > > + /* The below doubles as a POSTING_READ */ > > = > > Are we sure? ;) > > = > > > gen6_gt_check_fifodbg(dev_priv); > = > Well it does a read first thing so I think so. But does it read the right magic register? Referring to the magic ECOBUS mess we had earlier. But if this code actually works, then I guess we can be happy. -- = Ville Syrj=E4l=E4 Intel OTC