From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 06/15] drm/i915: there's no DSPSIZE register on gen4+ Date: Thu, 7 Mar 2013 11:38:24 +0200 Message-ID: <20130307093824.GS4469@intel.com> References: <1362611003-4823-1-git-send-email-przanoni@gmail.com> <1362611003-4823-7-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 3C5ABE5DBB for ; Thu, 7 Mar 2013 01:38:28 -0800 (PST) Content-Disposition: inline In-Reply-To: <1362611003-4823-7-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Paulo Zanoni Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org On Wed, Mar 06, 2013 at 08:03:13PM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni > = > So don't read it when capturing the error state. This solves some > "unclaimed register" messages on Haswell when we hang the GPU. You're sure about gen4? I haven't really checked but my impression is that gen4 is more like gen3, and gen4.5 more like gen5 as far as the display is concerned (eg. gen4 would have the old video overlay, and 4.5 would have video sprites). Can anyone confirm? > = > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/intel_display.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index 789a95a..56cca6e 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -9348,7 +9348,8 @@ intel_display_capture_error_state(struct drm_device= *dev) > = > error->plane[i].control =3D I915_READ(DSPCNTR(i)); > error->plane[i].stride =3D I915_READ(DSPSTRIDE(i)); > - error->plane[i].size =3D I915_READ(DSPSIZE(i)); > + if (INTEL_INFO(dev)->gen <=3D 3) > + error->plane[i].size =3D I915_READ(DSPSIZE(i)); > error->plane[i].pos =3D I915_READ(DSPPOS(i)); > error->plane[i].addr =3D I915_READ(DSPADDR(i)); > if (INTEL_INFO(dev)->gen >=3D 4) { > @@ -9392,7 +9393,8 @@ intel_display_print_error_state(struct seq_file *m, > seq_printf(m, "Plane [%d]:\n", i); > seq_printf(m, " CNTR: %08x\n", error->plane[i].control); > seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); > - seq_printf(m, " SIZE: %08x\n", error->plane[i].size); > + if (INTEL_INFO(dev)->gen <=3D 3) > + seq_printf(m, " SIZE: %08x\n", error->plane[i].size); > seq_printf(m, " POS: %08x\n", error->plane[i].pos); > seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); > if (INTEL_INFO(dev)->gen >=3D 4) { > -- = > 1.7.10.4 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC