From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ben Widawsky <ben@bwidawsk.net>
Subject: Re: [PATCH 08/15] drm/i915: remove DSPPOS register
Date: Fri, 15 Mar 2013 12:13:13 -0700
Message-ID: <20130315191313.GJ17773@bwidawsk.net>
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To: Paulo Zanoni <przanoni@gmail.com>
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On Wed, Mar 06, 2013 at 08:03:15PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> I couldn't find any evidence that this register exists on Gen2+. On
> Gen 2/3/4 documents this register is listed as reserved and read-only.
> On the newer Gens this register is not even documented.
> 
> Also all we do with this register is:
>   - Write 0 to it on i9xx_crtc_mode_set
>   - Save/restore its value on the UMS code
>   - Read it on intel_display_capture_error_state
> 
> This commit fixes "unclaimed register" messages when there's a GPU
> hang on Haswell.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
[snip]

-- 
Ben Widawsky, Intel Open Source Technology Center