From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 06/15] drm/i915: there's no DSPSIZE register
 on gen4+
Date: Sun, 17 Mar 2013 21:29:57 +0100
Message-ID: <20130317202957.GM9021@phenom.ffwll.local>
References: <1362611003-4823-1-git-send-email-przanoni@gmail.com>
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	<20130307093824.GS4469@intel.com>
	<20130315190411.GG17773@bwidawsk.net>
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To: Ben Widawsky <ben@bwidawsk.net>
Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni <paulo.r.zanoni@intel.com>
List-Id: intel-gfx@lists.freedesktop.org

On Fri, Mar 15, 2013 at 12:08:10PM -0700, Ben Widawsky wrote:
> On Fri, Mar 15, 2013 at 12:04:11PM -0700, Ben Widawsky wrote:
> > On Thu, Mar 07, 2013 at 11:38:24AM +0200, Ville Syrj=E4l=E4 wrote:
> > > On Wed, Mar 06, 2013 at 08:03:13PM -0300, Paulo Zanoni wrote:
> > > > From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > > =

> > > > So don't read it when capturing the error state. This solves some
> > > > "unclaimed register" messages on Haswell when we hang the GPU.
> > > =

> > > You're sure about gen4? I haven't really checked but my impression is
> > > that gen4 is more like gen3, and gen4.5 more like gen5 as far as the
> > > display is concerned (eg. gen4 would have the old video overlay, and
> > > 4.5 would have video sprites). Can anyone confirm?
> > =

> > This register isn't anywhere in modern docs, what's up?
> =

> Ooops, inverted the logic in my head. If you make the check for gen <=3D6
> which I can lazily check with modern docs:
> Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

I've also checked vanilla gen4 docs and that offset is already marked as
reserved, so we're good here.

Queued for -next, thanks for the patch.
-Daniel
-- =

Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch