[PATCHv2 2/2] ARM: socfpga: Add clock entries into device tree

[pavel@denx.de (Pavel Machek)]

Hi!

> Adds the main PLL clock groups for SOCFPGA into device tree file
> so that the clock framework to query the clock and clock rates
> appropriately.

Is there an easy way to test it?

I was keeping modified clk.c with hardcoded clock to have working
ethernet; I reverted that patch and applied 2/2, but now NFS root
refuses to mount (similar symptoms to missing clk.c modifications).

Also I need following patch to get it to compile:

commit f85232eec5330e64984facd300ef864c53a326f5
Author: Pavel Machek <pavel@pollux.denx.de>
Date:   Wed Mar 20 14:41:59 2013 +0100

    Patch needed to get clk.c to compile.
    
    Signed-off-by: Pavel Machek <pavel@denx.de>

diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c
index da6b461..3504dbf 100644
--- a/drivers/clk/socfpga/clk.c
+++ b/drivers/clk/socfpga/clk.c
@@ -49,6 +49,7 @@ struct socfpga_clk {
 	void __iomem *reg;
 	char *parent_name;
 	char *clk_name;
+	int fixed_div;
 };
 #define to_socfpga_clk(p) container_of(p, struct socfpga_clk, hw)
 

Thanks,
									Pavel
-- 
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